From a259712ccb53a2b59fc66e01646db9ce95167ab1 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Thu, 1 Sep 2022 20:33:36 +0200
Subject: testsuite/synth: improve test #1460

---
 testsuite/synth/issue1460/testsuite.sh    |  1 +
 testsuite/synth/issue1460/to01_float.vhdl | 17 +++++++++++++++++
 2 files changed, 18 insertions(+)
 create mode 100644 testsuite/synth/issue1460/to01_float.vhdl

(limited to 'testsuite')

diff --git a/testsuite/synth/issue1460/testsuite.sh b/testsuite/synth/issue1460/testsuite.sh
index a0520d8bb..b3b2efd6c 100755
--- a/testsuite/synth/issue1460/testsuite.sh
+++ b/testsuite/synth/issue1460/testsuite.sh
@@ -8,6 +8,7 @@ for t in leftmost01 leftmost02 leftmost03 rightmost01 rightmost02; do
     synth_tb $t
 done
 
+synth_analyze to01_float
 synth_analyze division_float
 
 echo "Test successful"
diff --git a/testsuite/synth/issue1460/to01_float.vhdl b/testsuite/synth/issue1460/to01_float.vhdl
new file mode 100644
index 000000000..234438e71
--- /dev/null
+++ b/testsuite/synth/issue1460/to01_float.vhdl
@@ -0,0 +1,17 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.float_pkg.all;
+
+entity to01_float is 
+port(
+i0 : in  float (7 downto -6);
+p0 : out float (7 downto -6));
+end to01_float ;
+
+architecture arch1 of to01_float is 
+
+begin
+--  p0 <= to_01(i0);
+  p0 <= UNRESOLVED_float (STD_LOGIC_VECTOR(to_01(UNSIGNED(to_sulv(i0)))));
+end arch1;
-- 
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