From 9e589aa557334c56af0b180341ce490da96980b3 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Thu, 28 Jul 2022 07:45:46 +0200
Subject: testsuite/gna: add a test for #2141

---
 testsuite/gna/issue2141/test.vhdl    | 35 +++++++++++++++++++++++++++++++++++
 testsuite/gna/issue2141/test2.vhdl   | 35 +++++++++++++++++++++++++++++++++++
 testsuite/gna/issue2141/test3.vhdl   | 35 +++++++++++++++++++++++++++++++++++
 testsuite/gna/issue2141/testsuite.sh | 14 ++++++++++++++
 4 files changed, 119 insertions(+)
 create mode 100644 testsuite/gna/issue2141/test.vhdl
 create mode 100644 testsuite/gna/issue2141/test2.vhdl
 create mode 100644 testsuite/gna/issue2141/test3.vhdl
 create mode 100755 testsuite/gna/issue2141/testsuite.sh

(limited to 'testsuite')

diff --git a/testsuite/gna/issue2141/test.vhdl b/testsuite/gna/issue2141/test.vhdl
new file mode 100644
index 000000000..1efd36a40
--- /dev/null
+++ b/testsuite/gna/issue2141/test.vhdl
@@ -0,0 +1,35 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity test is
+end;
+
+architecture BHV of test is
+  type array_t       is array( natural range <> ) of bit_vector;
+  type arry_arry_t   is array( natural range <> ) of array_t;
+
+  function get_min( a : arry_arry_t) return bit_vector is
+    --variable res    : a'element'element; -- fail@AHDL
+    --variable res    : bit_vector(a'element'element'range); -- success@AHDL
+      variable res : bit_vector(7 downto 0); -- success@GHDL
+    begin
+      res:=a(a'left)(a'element'left);
+      for i in a'range loop
+        for j in a'element'range loop
+          if (a(i)(j)<res) then
+            res:=a(i)(j);
+          end if;
+        end loop;
+      end loop;
+      return res;
+    end function get_min;
+
+  signal m2x2  : arry_arry_t(0 to 1)(0 to 1)(7 downto 0):=((x"01",x"02"),(x"80",x"10"));
+    signal m_min : m2x2'element'element; -- success@AHDL
+  --signal m_min : bit_vector(7 downto 0); -- success@GHDL
+
+begin
+
+  m_min <= get_min(m2x2);
+
+end;
diff --git a/testsuite/gna/issue2141/test2.vhdl b/testsuite/gna/issue2141/test2.vhdl
new file mode 100644
index 000000000..c065dc464
--- /dev/null
+++ b/testsuite/gna/issue2141/test2.vhdl
@@ -0,0 +1,35 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity test2 is
+end;
+
+architecture BHV of test2 is
+  type array_t       is array( natural range <> ) of bit_vector;
+  type arry_arry_t   is array( natural range <> ) of array_t;
+
+  function get_min( a : arry_arry_t) return bit_vector is
+    --variable res    : a'element'element; -- fail@AHDL
+      variable res    : bit_vector(a'element'element'range); -- success@AHDL
+    --variable res : bit_vector(7 downto 0); -- success@GHDL
+    begin
+      res:=a(a'left)(a'element'left);
+      for i in a'range loop
+        for j in a'element'range loop
+          if (a(i)(j)<res) then
+            res:=a(i)(j);
+          end if;
+        end loop;
+      end loop;
+      return res;
+    end function get_min;
+
+  signal m2x2  : arry_arry_t(0 to 1)(0 to 1)(7 downto 0):=((x"01",x"02"),(x"80",x"10"));
+    signal m_min : m2x2'element'element; -- success@AHDL
+  --signal m_min : bit_vector(7 downto 0); -- success@GHDL
+
+begin
+
+  m_min <= get_min(m2x2);
+
+end;
diff --git a/testsuite/gna/issue2141/test3.vhdl b/testsuite/gna/issue2141/test3.vhdl
new file mode 100644
index 000000000..61519d9e8
--- /dev/null
+++ b/testsuite/gna/issue2141/test3.vhdl
@@ -0,0 +1,35 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity test3 is
+end;
+
+architecture BHV of test3 is
+  type array_t       is array( natural range <> ) of bit_vector;
+  type arry_arry_t   is array( natural range <> ) of array_t;
+
+  function get_min( a : arry_arry_t) return bit_vector is
+      variable res    : a'element'element; -- fail@AHDL
+    --variable res    : bit_vector(a'element'element'range); -- success@AHDL
+    --variable res : bit_vector(7 downto 0); -- success@GHDL
+    begin
+      res:=a(a'left)(a'element'left);
+      for i in a'range loop
+        for j in a'element'range loop
+          if (a(i)(j)<res) then
+            res:=a(i)(j);
+          end if;
+        end loop;
+      end loop;
+      return res;
+    end function get_min;
+
+  signal m2x2  : arry_arry_t(0 to 1)(0 to 1)(7 downto 0):=((x"01",x"02"),(x"80",x"10"));
+    signal m_min : m2x2'element'element; -- success@AHDL
+  --signal m_min : bit_vector(7 downto 0); -- success@GHDL
+
+begin
+
+  m_min <= get_min(m2x2);
+
+end;
diff --git a/testsuite/gna/issue2141/testsuite.sh b/testsuite/gna/issue2141/testsuite.sh
new file mode 100755
index 000000000..4820b6d2c
--- /dev/null
+++ b/testsuite/gna/issue2141/testsuite.sh
@@ -0,0 +1,14 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+
+for f in test test2 test3; do
+    analyze $f.vhdl
+    elab_simulate $f
+done
+
+clean
+
+echo "Test successful"
-- 
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