From 96f5e9b58e5c96ee1a9540c49bb573cccadee67d Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Wed, 1 Nov 2017 06:24:38 +0100 Subject: Add reproducer for #418 --- testsuite/gna/issue418/repro.vhdl | 76 +++++++++++++++++++++++++++++++++++++ testsuite/gna/issue418/repro2.notes | 25 ++++++++++++ testsuite/gna/issue418/repro2.vhdl | 35 +++++++++++++++++ testsuite/gna/issue418/testsuite.sh | 25 ++++++++++++ 4 files changed, 161 insertions(+) create mode 100644 testsuite/gna/issue418/repro.vhdl create mode 100644 testsuite/gna/issue418/repro2.notes create mode 100644 testsuite/gna/issue418/repro2.vhdl create mode 100755 testsuite/gna/issue418/testsuite.sh (limited to 'testsuite') diff --git a/testsuite/gna/issue418/repro.vhdl b/testsuite/gna/issue418/repro.vhdl new file mode 100644 index 000000000..1d0c625bd --- /dev/null +++ b/testsuite/gna/issue418/repro.vhdl @@ -0,0 +1,76 @@ +entity repro is +end; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of repro is + -- AXI-Lite Interface signals + type t_axilite_write_address_channel is record + --DUT inputs + awaddr : std_logic_vector; + awvalid : std_logic; + awprot : std_logic_vector(2 downto 0); -- [0: '0' - unpriviliged access, '1' - priviliged access; 1: '0' - secure access, '1' - non-secure access, 2: '0' - Data access, '1' - Instruction accesss] + --DUT outputs + awready : std_logic; + end record; + + type t_axilite_write_data_channel is record + --DUT inputs + wdata : std_logic_vector; + wstrb : std_logic_vector; + wvalid : std_logic; + --DUT outputs + wready : std_logic; + end record; + + type t_axilite_write_response_channel is record + --DUT inputs + bready : std_logic; + --DUT outputs + bresp : std_logic_vector(1 downto 0); + bvalid : std_logic; + end record; + + type t_axilite_read_address_channel is record + --DUT inputs + araddr : std_logic_vector; + arvalid : std_logic; + arprot : std_logic_vector(2 downto 0); -- [0: '0' - unpriviliged access, '1' - priviliged access; 1: '0' - secure access, '1' - non-secure access, 2: '0' - Data access, '1' - Instruction accesss] + --DUT outputs + arready : std_logic; + end record; + + type t_axilite_read_data_channel is record + --DUT inputs + rready : std_logic; + --DUT outputs + rdata : std_logic_vector; + rresp : std_logic_vector(1 downto 0); + rvalid : std_logic; + end record; + + type t_axilite_if is record + write_address_channel : t_axilite_write_address_channel; + write_data_channel : t_axilite_write_data_channel; + write_response_channel : t_axilite_write_response_channel; + read_address_channel : t_axilite_read_address_channel; + read_data_channel : t_axilite_read_data_channel; + end record; + + subtype ST_AXILite_32 is t_axilite_if ( + write_address_channel ( + awaddr(31 downto 0) ), + write_data_channel ( + wdata(31 downto 0), + wstrb(3 downto 0) ), + read_address_channel ( + araddr(31 downto 0) ), + read_data_channel ( + rdata(31 downto 0) ) + ); + + signal s : st_axilite_32; +begin + s.write_address_channel.awaddr <= x"0000_1000", x"1000_ffff" after 2 ns; +end; diff --git a/testsuite/gna/issue418/repro2.notes b/testsuite/gna/issue418/repro2.notes new file mode 100644 index 000000000..02bf0f30e --- /dev/null +++ b/testsuite/gna/issue418/repro2.notes @@ -0,0 +1,25 @@ + type address_channel is record + awaddr : bit_vector; + awvalid : bit; + end record; + + type t_if is record + write_channel : address_channel; + end record; + + subtype ST_IF_32 is t_if (write_channel (awaddr(31 downto 0))); + + +TYPE work__repro2__ARCH__behav__address_channel__SIGBASE IS RECORD + awaddr: __ghdl_index_type; + awvalid: __ghdl_signal_ptr; +END RECORD; + +TYPE work__repro2__ARCH__behav__t_if__SIGBASE IS RECORD + write_channel: __ghdl_index_type; +END RECORD; + +TYPE work__repro2__ARCH__behav__st_if_32__SIG IS RECORD + BASE: work__repro2__ARCH__behav__t_if__SIGBASE; + write_channel: work__repro2__ARCH__behav__st_if_32__write_channel__SIG; +END RECORD; diff --git a/testsuite/gna/issue418/repro2.vhdl b/testsuite/gna/issue418/repro2.vhdl new file mode 100644 index 000000000..9565c86ee --- /dev/null +++ b/testsuite/gna/issue418/repro2.vhdl @@ -0,0 +1,35 @@ +entity repro2 is +end; + +architecture behav of repro2 is + -- AXI-Lite Interface signals + type address_channel is record + --DUT inputs + awaddr : bit_vector; + awvalid : bit; + end record; + + + type t_if is record + write_channel : address_channel; + end record; + + subtype ST_IF_32 is t_if ( + write_channel ( + awaddr(31 downto 0) ) + ); + + signal s : st_if_32; +begin + s.write_channel.awaddr <= x"0000_1000", x"1000_ffff" after 2 ns; + process + begin + wait for 1 ns; + assert s.write_channel.awvalid = '0'; + assert s.write_channel.awaddr(12) = '1'; + wait for 2 ns; + assert s.write_channel.awaddr(14) = '1'; + wait; + end process; + +end; diff --git a/testsuite/gna/issue418/testsuite.sh b/testsuite/gna/issue418/testsuite.sh new file mode 100755 index 000000000..86c375820 --- /dev/null +++ b/testsuite/gna/issue418/testsuite.sh @@ -0,0 +1,25 @@ +#! /bin/sh + +. ../../testenv.sh + +export GHDL_STD_FLAGS=--std=08 +analyze repro.vhdl +elab repro + +if ghdl_has_feature repro ghw; then + simulate repro --wave=repro.ghw + # How to test the ghw ? Use ghwdump ? +fi + +analyze repro2.vhdl +elab repro2 + +if ghdl_has_feature repro2 ghw; then + simulate repro2 --wave=repro2.ghw + # How to test the ghw ? Use ghwdump ? +fi + +clean +rm -f repro.ghw repro2.ghw + +echo "Test successful" -- cgit v1.2.3