From 7f703bfbb31f24c84d0b224aeb3613692bddf214 Mon Sep 17 00:00:00 2001
From: Patrick Lehmann <Patrick.Lehmann@plc2.de>
Date: Mon, 28 Dec 2020 18:15:03 +0100
Subject: Renamed testcase to SimpleEntity.

---
 testsuite/pyunit/SimpleEntity.vhdl         | 27 +++++++++++++++++++++++++++
 testsuite/pyunit/dom/Instantiate.py        | 25 -------------------------
 testsuite/pyunit/dom/SimpleEntity.py       | 25 +++++++++++++++++++++++++
 testsuite/pyunit/libghdl/simpleEntity.vhdl | 27 ---------------------------
 4 files changed, 52 insertions(+), 52 deletions(-)
 create mode 100644 testsuite/pyunit/SimpleEntity.vhdl
 delete mode 100644 testsuite/pyunit/dom/Instantiate.py
 create mode 100644 testsuite/pyunit/dom/SimpleEntity.py
 delete mode 100644 testsuite/pyunit/libghdl/simpleEntity.vhdl

(limited to 'testsuite')

diff --git a/testsuite/pyunit/SimpleEntity.vhdl b/testsuite/pyunit/SimpleEntity.vhdl
new file mode 100644
index 000000000..a26a6357c
--- /dev/null
+++ b/testsuite/pyunit/SimpleEntity.vhdl
@@ -0,0 +1,27 @@
+library ieee;
+use     ieee.numeric_std.all;
+
+entity e1 is
+	generic (
+		BITS : positive := 8
+	);
+	port (
+	  Clock: in  std_logic;
+	  Reset: in  std_logic;
+	  Q:     out std_logic_vector(BITS - 1 downto 0)
+	);
+end entity e1;
+
+architecture behav of e1 is
+begin
+	process(Clock)
+	begin
+		if rising_edge(Clock) then
+			if Reset = '1' then
+				Q <= (others => '0');
+			else
+				Q <= std_logic_vector(unsigned(Q) + 1);
+			end if;
+		end if;
+	end process;
+end architecture behav;
diff --git a/testsuite/pyunit/dom/Instantiate.py b/testsuite/pyunit/dom/Instantiate.py
deleted file mode 100644
index 429c1a5a8..000000000
--- a/testsuite/pyunit/dom/Instantiate.py
+++ /dev/null
@@ -1,25 +0,0 @@
-from pathlib  import Path
-from unittest import TestCase
-
-from pyVHDLModel.VHDLModel import Design, Library, Document, Entity
-
-
-if __name__ == "__main__":
-	print("ERROR: you called a testcase declaration file as an executable module.")
-	print("Use: 'python -m unitest <testcase module>'")
-	exit(1)
-
-
-class Instantiate(TestCase):
-	def test_Design(self):
-		design = Design()
-
-	def test_Library(self):
-		library = Library()
-
-	def test_Document(self):
-		path = Path("tests.vhdl")
-		document = Document(path)
-
-	def test_Entity(self):
-		entity = Entity("entity_1")
diff --git a/testsuite/pyunit/dom/SimpleEntity.py b/testsuite/pyunit/dom/SimpleEntity.py
new file mode 100644
index 000000000..429c1a5a8
--- /dev/null
+++ b/testsuite/pyunit/dom/SimpleEntity.py
@@ -0,0 +1,25 @@
+from pathlib  import Path
+from unittest import TestCase
+
+from pyVHDLModel.VHDLModel import Design, Library, Document, Entity
+
+
+if __name__ == "__main__":
+	print("ERROR: you called a testcase declaration file as an executable module.")
+	print("Use: 'python -m unitest <testcase module>'")
+	exit(1)
+
+
+class Instantiate(TestCase):
+	def test_Design(self):
+		design = Design()
+
+	def test_Library(self):
+		library = Library()
+
+	def test_Document(self):
+		path = Path("tests.vhdl")
+		document = Document(path)
+
+	def test_Entity(self):
+		entity = Entity("entity_1")
diff --git a/testsuite/pyunit/libghdl/simpleEntity.vhdl b/testsuite/pyunit/libghdl/simpleEntity.vhdl
deleted file mode 100644
index a26a6357c..000000000
--- a/testsuite/pyunit/libghdl/simpleEntity.vhdl
+++ /dev/null
@@ -1,27 +0,0 @@
-library ieee;
-use     ieee.numeric_std.all;
-
-entity e1 is
-	generic (
-		BITS : positive := 8
-	);
-	port (
-	  Clock: in  std_logic;
-	  Reset: in  std_logic;
-	  Q:     out std_logic_vector(BITS - 1 downto 0)
-	);
-end entity e1;
-
-architecture behav of e1 is
-begin
-	process(Clock)
-	begin
-		if rising_edge(Clock) then
-			if Reset = '1' then
-				Q <= (others => '0');
-			else
-				Q <= std_logic_vector(unsigned(Q) + 1);
-			end if;
-		end if;
-	end process;
-end architecture behav;
-- 
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