From 7064ef37029a883d0098d0af665231b36854d5e2 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Thu, 9 Jun 2022 05:34:37 +0200
Subject: testsuite/synth: add a test for #2084

---
 testsuite/synth/issue2084/bug.vhdl     | 15 +++++++++++++++
 testsuite/synth/issue2084/testsuite.sh |  8 ++++++++
 2 files changed, 23 insertions(+)
 create mode 100644 testsuite/synth/issue2084/bug.vhdl
 create mode 100755 testsuite/synth/issue2084/testsuite.sh

(limited to 'testsuite')

diff --git a/testsuite/synth/issue2084/bug.vhdl b/testsuite/synth/issue2084/bug.vhdl
new file mode 100644
index 000000000..847ac0f1b
--- /dev/null
+++ b/testsuite/synth/issue2084/bug.vhdl
@@ -0,0 +1,15 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity bug is
+	port (
+		src : in std_ulogic_vector(31 downto 0)
+	);
+end bug;
+
+architecture rtl of bug is
+	type array_t is array(0 to 0) of src'subtype;
+	signal s : array_t;
+begin
+
+end architecture;
diff --git a/testsuite/synth/issue2084/testsuite.sh b/testsuite/synth/issue2084/testsuite.sh
new file mode 100755
index 000000000..c355095b7
--- /dev/null
+++ b/testsuite/synth/issue2084/testsuite.sh
@@ -0,0 +1,8 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=--std=08
+synth_only bug
+
+echo "Test successful"
-- 
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