From 6e9336d11dfc4f53dba234e1f02a2b0172461e0c Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Wed, 25 Sep 2019 20:39:46 +0200 Subject: testsuite/synth: rename issueXX to synthXX for ghdlsynth-beta issues. --- testsuite/synth/issue12/lut.vhdl | 25 ----------- testsuite/synth/issue12/tb_lut.vhdl | 34 --------------- testsuite/synth/issue12/testsuite.sh | 16 ------- testsuite/synth/issue26/int_test.vhdl | 20 --------- testsuite/synth/issue26/testsuite.sh | 9 ---- testsuite/synth/issue27/dff.vhdl | 40 ----------------- testsuite/synth/issue27/testsuite.sh | 8 ---- testsuite/synth/issue33/int_test.vhdl | 31 ------------- testsuite/synth/issue33/int_test2.vhdl | 31 ------------- testsuite/synth/issue33/testsuite.sh | 11 ----- testsuite/synth/issue34/module.vhdl | 20 --------- testsuite/synth/issue34/repro_nat.vhdl | 42 ------------------ testsuite/synth/issue34/repro_rng1.vhdl | 42 ------------------ testsuite/synth/issue34/repro_sgn.vhdl | 44 ------------------- testsuite/synth/issue34/repro_slv.vhdl | 42 ------------------ testsuite/synth/issue34/repro_uns.vhdl | 44 ------------------- testsuite/synth/issue34/submodule.vhdl | 20 --------- testsuite/synth/issue34/tb_repro_nat.vhdl | 34 --------------- testsuite/synth/issue34/tb_repro_rng1.vhdl | 34 --------------- testsuite/synth/issue34/tb_repro_sgn.vhdl | 35 --------------- testsuite/synth/issue34/tb_repro_slv.vhdl | 34 --------------- testsuite/synth/issue34/tb_repro_uns.vhdl | 35 --------------- testsuite/synth/issue34/testsuite.sh | 16 ------- testsuite/synth/issue39/rec2.vhdl | 43 ------------------ testsuite/synth/issue39/record_test.vhdl | 43 ------------------ testsuite/synth/issue39/tb_rec2.vhdl | 65 ---------------------------- testsuite/synth/issue39/tb_record_test.vhdl | 65 ---------------------------- testsuite/synth/issue39/testsuite.sh | 16 ------- testsuite/synth/issue40/tb_testcase.vhdl | 26 ----------- testsuite/synth/issue40/testcase.vhdl | 17 -------- testsuite/synth/issue40/testsuite.sh | 18 -------- testsuite/synth/issue8/tb_test5.vhdl | 19 -------- testsuite/synth/issue8/tb_vector8_test1.vhdl | 19 -------- testsuite/synth/issue8/test2.vhdl | 15 ------- testsuite/synth/issue8/test3.vhdl | 28 ------------ testsuite/synth/issue8/test4.vhdl | 28 ------------ testsuite/synth/issue8/test5.vhdl | 15 ------- testsuite/synth/issue8/testsuite.sh | 16 ------- testsuite/synth/issue8/vector8_test1.vhdl | 16 ------- testsuite/synth/synth12/lut.vhdl | 25 +++++++++++ testsuite/synth/synth12/tb_lut.vhdl | 34 +++++++++++++++ testsuite/synth/synth12/testsuite.sh | 16 +++++++ testsuite/synth/synth26/int_test.vhdl | 20 +++++++++ testsuite/synth/synth26/testsuite.sh | 9 ++++ testsuite/synth/synth27/dff.vhdl | 40 +++++++++++++++++ testsuite/synth/synth27/testsuite.sh | 8 ++++ testsuite/synth/synth33/int_test.vhdl | 31 +++++++++++++ testsuite/synth/synth33/int_test2.vhdl | 31 +++++++++++++ testsuite/synth/synth33/testsuite.sh | 11 +++++ testsuite/synth/synth34/module.vhdl | 20 +++++++++ testsuite/synth/synth34/repro_nat.vhdl | 42 ++++++++++++++++++ testsuite/synth/synth34/repro_rng1.vhdl | 42 ++++++++++++++++++ testsuite/synth/synth34/repro_sgn.vhdl | 44 +++++++++++++++++++ testsuite/synth/synth34/repro_slv.vhdl | 42 ++++++++++++++++++ testsuite/synth/synth34/repro_uns.vhdl | 44 +++++++++++++++++++ testsuite/synth/synth34/submodule.vhdl | 20 +++++++++ testsuite/synth/synth34/tb_repro_nat.vhdl | 34 +++++++++++++++ testsuite/synth/synth34/tb_repro_rng1.vhdl | 34 +++++++++++++++ testsuite/synth/synth34/tb_repro_sgn.vhdl | 35 +++++++++++++++ testsuite/synth/synth34/tb_repro_slv.vhdl | 34 +++++++++++++++ testsuite/synth/synth34/tb_repro_uns.vhdl | 35 +++++++++++++++ testsuite/synth/synth34/testsuite.sh | 16 +++++++ testsuite/synth/synth39/rec2.vhdl | 43 ++++++++++++++++++ testsuite/synth/synth39/record_test.vhdl | 43 ++++++++++++++++++ testsuite/synth/synth39/tb_rec2.vhdl | 65 ++++++++++++++++++++++++++++ testsuite/synth/synth39/tb_record_test.vhdl | 65 ++++++++++++++++++++++++++++ testsuite/synth/synth39/testsuite.sh | 16 +++++++ testsuite/synth/synth40/tb_testcase.vhdl | 26 +++++++++++ testsuite/synth/synth40/testcase.vhdl | 17 ++++++++ testsuite/synth/synth40/testsuite.sh | 18 ++++++++ testsuite/synth/synth8/tb_test5.vhdl | 19 ++++++++ testsuite/synth/synth8/tb_vector8_test1.vhdl | 19 ++++++++ testsuite/synth/synth8/test2.vhdl | 15 +++++++ testsuite/synth/synth8/test3.vhdl | 28 ++++++++++++ testsuite/synth/synth8/test4.vhdl | 28 ++++++++++++ testsuite/synth/synth8/test5.vhdl | 15 +++++++ testsuite/synth/synth8/testsuite.sh | 16 +++++++ testsuite/synth/synth8/vector8_test1.vhdl | 16 +++++++ 78 files changed, 1116 insertions(+), 1116 deletions(-) delete mode 100644 testsuite/synth/issue12/lut.vhdl delete mode 100644 testsuite/synth/issue12/tb_lut.vhdl delete mode 100755 testsuite/synth/issue12/testsuite.sh delete mode 100644 testsuite/synth/issue26/int_test.vhdl delete mode 100755 testsuite/synth/issue26/testsuite.sh delete mode 100644 testsuite/synth/issue27/dff.vhdl delete mode 100755 testsuite/synth/issue27/testsuite.sh delete mode 100644 testsuite/synth/issue33/int_test.vhdl delete mode 100644 testsuite/synth/issue33/int_test2.vhdl delete mode 100755 testsuite/synth/issue33/testsuite.sh delete mode 100644 testsuite/synth/issue34/module.vhdl delete mode 100644 testsuite/synth/issue34/repro_nat.vhdl delete mode 100644 testsuite/synth/issue34/repro_rng1.vhdl delete mode 100644 testsuite/synth/issue34/repro_sgn.vhdl delete mode 100644 testsuite/synth/issue34/repro_slv.vhdl delete mode 100644 testsuite/synth/issue34/repro_uns.vhdl delete mode 100644 testsuite/synth/issue34/submodule.vhdl delete mode 100644 testsuite/synth/issue34/tb_repro_nat.vhdl delete mode 100644 testsuite/synth/issue34/tb_repro_rng1.vhdl delete mode 100644 testsuite/synth/issue34/tb_repro_sgn.vhdl delete mode 100644 testsuite/synth/issue34/tb_repro_slv.vhdl delete mode 100644 testsuite/synth/issue34/tb_repro_uns.vhdl delete mode 100755 testsuite/synth/issue34/testsuite.sh delete mode 100644 testsuite/synth/issue39/rec2.vhdl delete mode 100644 testsuite/synth/issue39/record_test.vhdl delete mode 100644 testsuite/synth/issue39/tb_rec2.vhdl delete mode 100644 testsuite/synth/issue39/tb_record_test.vhdl delete mode 100755 testsuite/synth/issue39/testsuite.sh delete mode 100644 testsuite/synth/issue40/tb_testcase.vhdl delete mode 100644 testsuite/synth/issue40/testcase.vhdl delete mode 100755 testsuite/synth/issue40/testsuite.sh delete mode 100644 testsuite/synth/issue8/tb_test5.vhdl delete mode 100644 testsuite/synth/issue8/tb_vector8_test1.vhdl delete mode 100644 testsuite/synth/issue8/test2.vhdl delete mode 100644 testsuite/synth/issue8/test3.vhdl delete mode 100644 testsuite/synth/issue8/test4.vhdl delete mode 100644 testsuite/synth/issue8/test5.vhdl delete mode 100755 testsuite/synth/issue8/testsuite.sh delete mode 100644 testsuite/synth/issue8/vector8_test1.vhdl create mode 100644 testsuite/synth/synth12/lut.vhdl create mode 100644 testsuite/synth/synth12/tb_lut.vhdl create mode 100755 testsuite/synth/synth12/testsuite.sh create mode 100644 testsuite/synth/synth26/int_test.vhdl create mode 100755 testsuite/synth/synth26/testsuite.sh create mode 100644 testsuite/synth/synth27/dff.vhdl create mode 100755 testsuite/synth/synth27/testsuite.sh create mode 100644 testsuite/synth/synth33/int_test.vhdl create mode 100644 testsuite/synth/synth33/int_test2.vhdl create mode 100755 testsuite/synth/synth33/testsuite.sh create mode 100644 testsuite/synth/synth34/module.vhdl create mode 100644 testsuite/synth/synth34/repro_nat.vhdl create mode 100644 testsuite/synth/synth34/repro_rng1.vhdl create mode 100644 testsuite/synth/synth34/repro_sgn.vhdl create mode 100644 testsuite/synth/synth34/repro_slv.vhdl create mode 100644 testsuite/synth/synth34/repro_uns.vhdl create mode 100644 testsuite/synth/synth34/submodule.vhdl create mode 100644 testsuite/synth/synth34/tb_repro_nat.vhdl create mode 100644 testsuite/synth/synth34/tb_repro_rng1.vhdl create mode 100644 testsuite/synth/synth34/tb_repro_sgn.vhdl create mode 100644 testsuite/synth/synth34/tb_repro_slv.vhdl create mode 100644 testsuite/synth/synth34/tb_repro_uns.vhdl create mode 100755 testsuite/synth/synth34/testsuite.sh create mode 100644 testsuite/synth/synth39/rec2.vhdl create mode 100644 testsuite/synth/synth39/record_test.vhdl create mode 100644 testsuite/synth/synth39/tb_rec2.vhdl create mode 100644 testsuite/synth/synth39/tb_record_test.vhdl create mode 100755 testsuite/synth/synth39/testsuite.sh create mode 100644 testsuite/synth/synth40/tb_testcase.vhdl create mode 100644 testsuite/synth/synth40/testcase.vhdl create mode 100755 testsuite/synth/synth40/testsuite.sh create mode 100644 testsuite/synth/synth8/tb_test5.vhdl create mode 100644 testsuite/synth/synth8/tb_vector8_test1.vhdl create mode 100644 testsuite/synth/synth8/test2.vhdl create mode 100644 testsuite/synth/synth8/test3.vhdl create mode 100644 testsuite/synth/synth8/test4.vhdl create mode 100644 testsuite/synth/synth8/test5.vhdl create mode 100755 testsuite/synth/synth8/testsuite.sh create mode 100644 testsuite/synth/synth8/vector8_test1.vhdl (limited to 'testsuite') diff --git a/testsuite/synth/issue12/lut.vhdl b/testsuite/synth/issue12/lut.vhdl deleted file mode 100644 index 5c04e8d9a..000000000 --- a/testsuite/synth/issue12/lut.vhdl +++ /dev/null @@ -1,25 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; - -entity lut is port ( - sel: in std_logic_vector (1 downto 0); - c: out std_logic); -end lut; - --- sel(1) sel(0) | c --- 0 0 | 1 --- 0 1 | 0 --- 1 0 | 1 --- 1 1 | 0 - -architecture synth of lut is -begin - -with sel select c <= - - '1' when "00", - '0' when "01", - '1' when "10", - '0' when others; - -end synth; diff --git a/testsuite/synth/issue12/tb_lut.vhdl b/testsuite/synth/issue12/tb_lut.vhdl deleted file mode 100644 index f8f5cf3a6..000000000 --- a/testsuite/synth/issue12/tb_lut.vhdl +++ /dev/null @@ -1,34 +0,0 @@ -entity tb_lut is -end tb_lut; - -library ieee; -use ieee.std_logic_1164.all; - -architecture behav of tb_lut is - signal c : std_logic; - signal s : std_logic_vector(1 downto 0); -begin - dut: entity work.lut - port map (s, c); - - process - begin - s <= "00"; - wait for 1 ns; - assert c = '1' severity failure; - - s <= "01"; - wait for 1 ns; - assert c = '0' severity failure; - - s <= "10"; - wait for 1 ns; - assert c = '1' severity failure; - - s <= "11"; - wait for 1 ns; - assert c = '0' severity failure; - - wait; - end process; -end behav; diff --git a/testsuite/synth/issue12/testsuite.sh b/testsuite/synth/issue12/testsuite.sh deleted file mode 100755 index a65695152..000000000 --- a/testsuite/synth/issue12/testsuite.sh +++ /dev/null @@ -1,16 +0,0 @@ -#! /bin/sh - -. ../../testenv.sh - -for t in lut; do - analyze $t.vhdl tb_$t.vhdl - elab_simulate tb_$t - clean - - synth $t.vhdl -e $t > syn_$t.vhdl - analyze syn_$t.vhdl tb_$t.vhdl - elab_simulate tb_$t - clean -done - -echo "Test successful" diff --git a/testsuite/synth/issue26/int_test.vhdl b/testsuite/synth/issue26/int_test.vhdl deleted file mode 100644 index afc8c4cdb..000000000 --- a/testsuite/synth/issue26/int_test.vhdl +++ /dev/null @@ -1,20 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; - -entity int_test is - port (clk : in std_logic; - a, b : in integer range 0 to 1; - c : out std_logic); -end int_test; - -architecture rtl of int_test is -begin - process (clk) - begin - if rising_edge (clk) then - if a < b then - c <= '0'; - end if; - end if; - end process; -end rtl; diff --git a/testsuite/synth/issue26/testsuite.sh b/testsuite/synth/issue26/testsuite.sh deleted file mode 100755 index 1cc0536d7..000000000 --- a/testsuite/synth/issue26/testsuite.sh +++ /dev/null @@ -1,9 +0,0 @@ -#! /bin/sh - -. ../../testenv.sh - -synth int_test.vhdl -e int_test > syn_int_test.vhdl -analyze syn_int_test.vhdl -clean - -echo "Test successful" diff --git a/testsuite/synth/issue27/dff.vhdl b/testsuite/synth/issue27/dff.vhdl deleted file mode 100644 index 2bf3ebec8..000000000 --- a/testsuite/synth/issue27/dff.vhdl +++ /dev/null @@ -1,40 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; - -entity dff is - generic( - formal_g : boolean := true - ); - port( - reset : in std_logic; - clk : in std_logic; - d : in std_logic; - q : out std_logic - ); -end entity dff; - -architecture rtl of dff is - signal q_int : std_logic; -begin - - dff_proc : process(clk, reset) - begin - if reset = '1' then - q_int <= '0'; - elsif rising_edge(clk) then - q_int <= d; - end if; - end process dff_proc; - - -- drive q_int to output port - q <= q_int; - - formal_gen : if formal_g = true generate - begin - -- set all declarations to run on clk - default clock is rising_edge(clk); - d_in_check : assert always {d} |=> {q_int}; - not_d_in_check : assert always {not d} |=> {not q_int}; - end generate formal_gen; - -end rtl; diff --git a/testsuite/synth/issue27/testsuite.sh b/testsuite/synth/issue27/testsuite.sh deleted file mode 100755 index b5ed1a2b7..000000000 --- a/testsuite/synth/issue27/testsuite.sh +++ /dev/null @@ -1,8 +0,0 @@ -#! /bin/sh - -. ../../testenv.sh - -export GHDL_STD_FLAGS=--std=08 -synth dff.vhdl -e dff > syn_dff.vhdl - -echo "Test successful" diff --git a/testsuite/synth/issue33/int_test.vhdl b/testsuite/synth/issue33/int_test.vhdl deleted file mode 100644 index 62ea65bda..000000000 --- a/testsuite/synth/issue33/int_test.vhdl +++ /dev/null @@ -1,31 +0,0 @@ -library ieee; - use ieee.std_logic_1164.all; - -entity int_test is - generic ( - INT_MIN : integer range 1 to 8 := 1; - INT_MAX : integer range 1 to 8 := 8 - ); - port ( - clk : in std_logic; - a : in integer range INT_MIN to INT_MAX; - b : out integer range INT_MIN to INT_MAX - ); -end int_test; - -architecture rtl of int_test is - signal int : integer range INT_MIN to INT_MAX; -begin - process (clk) - begin - if rising_edge (clk) then - if a < INT_MAX then - int <= a + 1; - else - int <= INT_MIN; - end if; - end if; - end process; - b <= int; -end rtl; - diff --git a/testsuite/synth/issue33/int_test2.vhdl b/testsuite/synth/issue33/int_test2.vhdl deleted file mode 100644 index eb43306c4..000000000 --- a/testsuite/synth/issue33/int_test2.vhdl +++ /dev/null @@ -1,31 +0,0 @@ -library ieee; - use ieee.std_logic_1164.all; - -entity int_test2 is - generic ( - INT_MIN : integer range 1 to 8 := 1; - INT_MAX : integer range 1 to 8 := 8 - ); - port ( - clk : in std_logic; - a : in integer range INT_MIN to INT_MAX; - b : out integer range INT_MIN to INT_MAX - ); -end int_test2; - -architecture rtl of int_test2 is - signal int : integer range INT_MIN to INT_MAX; -begin - process (clk) - begin - if rising_edge (clk) then - if a < INT_MAX then - int <= a + 1; - else - int <= INT_MIN * 2; - end if; - end if; - end process; - b <= int; -end rtl; - diff --git a/testsuite/synth/issue33/testsuite.sh b/testsuite/synth/issue33/testsuite.sh deleted file mode 100755 index fca6f7d69..000000000 --- a/testsuite/synth/issue33/testsuite.sh +++ /dev/null @@ -1,11 +0,0 @@ -#! /bin/sh - -. ../../testenv.sh - -for t in int_test int_test2; do - synth $t.vhdl -e $t > syn_$t.vhdl - analyze syn_$t.vhdl - clean -done - -echo "Test successful" diff --git a/testsuite/synth/issue34/module.vhdl b/testsuite/synth/issue34/module.vhdl deleted file mode 100644 index 67f3dd4b3..000000000 --- a/testsuite/synth/issue34/module.vhdl +++ /dev/null @@ -1,20 +0,0 @@ -library ieee; - use ieee.std_logic_1164.all; - -entity module is - port ( - clk : in std_logic; - a : in std_logic_vector(7 downto 0); - b : out std_logic_vector(7 downto 0) - ); -end module; - -architecture rtl of module is -begin - i_submodule : entity work.submodule - port map ( - clk => clk, - a => a, - b => b - ); -end rtl; diff --git a/testsuite/synth/issue34/repro_nat.vhdl b/testsuite/synth/issue34/repro_nat.vhdl deleted file mode 100644 index 328c11781..000000000 --- a/testsuite/synth/issue34/repro_nat.vhdl +++ /dev/null @@ -1,42 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; - -entity sub_nat is - port ( - clk : in std_logic; - a : in natural; - b : out natural - ); -end sub_nat; - -architecture rtl of sub_nat is -begin - process(clk) - begin - if rising_edge(clk) then - b <= a; - end if; - end process; -end rtl; - - -library ieee; -use ieee.std_logic_1164.all; - -entity repro_nat is - port ( - clk : in std_logic; - a : in natural; - b : out natural - ); -end repro_nat; - -architecture rtl of repro_nat is -begin - i_sub_nat : entity work.sub_nat - port map ( - clk => clk, - a => a, - b => b - ); -end rtl; diff --git a/testsuite/synth/issue34/repro_rng1.vhdl b/testsuite/synth/issue34/repro_rng1.vhdl deleted file mode 100644 index 9d5a70e04..000000000 --- a/testsuite/synth/issue34/repro_rng1.vhdl +++ /dev/null @@ -1,42 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; - -entity sub_rng1 is - port ( - clk : in std_logic; - a : in natural range 0 to 7; - b : out natural range 0 to 7 - ); -end sub_rng1; - -architecture rtl of sub_rng1 is -begin - process(clk) - begin - if rising_edge(clk) then - b <= a; - end if; - end process; -end rtl; - - -library ieee; -use ieee.std_logic_1164.all; - -entity repro_rng1 is - port ( - clk : in std_logic; - a : in natural range 0 to 7; - b : out natural range 0 to 7 - ); -end repro_rng1; - -architecture rtl of repro_rng1 is -begin - i_sub_rng1 : entity work.sub_rng1 - port map ( - clk => clk, - a => a, - b => b - ); -end rtl; diff --git a/testsuite/synth/issue34/repro_sgn.vhdl b/testsuite/synth/issue34/repro_sgn.vhdl deleted file mode 100644 index fa23693d3..000000000 --- a/testsuite/synth/issue34/repro_sgn.vhdl +++ /dev/null @@ -1,44 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity sub_sgn is - port ( - clk : in std_logic; - a : in signed(7 downto 0); - b : out signed(7 downto 0) - ); -end sub_sgn; - -architecture rtl of sub_sgn is -begin - process(clk) - begin - if rising_edge(clk) then - b <= a; - end if; - end process; -end rtl; - - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity repro_sgn is - port ( - clk : in std_logic; - a : in signed(7 downto 0); - b : out signed(7 downto 0) - ); -end repro_sgn; - -architecture rtl of repro_sgn is -begin - i_sub_sgn : entity work.sub_sgn - port map ( - clk => clk, - a => a, - b => b - ); -end rtl; diff --git a/testsuite/synth/issue34/repro_slv.vhdl b/testsuite/synth/issue34/repro_slv.vhdl deleted file mode 100644 index 4b0e1b0e5..000000000 --- a/testsuite/synth/issue34/repro_slv.vhdl +++ /dev/null @@ -1,42 +0,0 @@ -library ieee; - use ieee.std_logic_1164.all; - -entity sub_slv is - port ( - clk : in std_logic; - a : in std_logic_vector(7 downto 0); - b : out std_logic_vector(7 downto 0) - ); -end sub_slv; - -architecture rtl of sub_slv is -begin - process(clk) - begin - if rising_edge(clk) then - b <= a; - end if; - end process; -end rtl; - - -library ieee; - use ieee.std_logic_1164.all; - -entity repro_slv is - port ( - clk : in std_logic; - a : in std_logic_vector(7 downto 0); - b : out std_logic_vector(7 downto 0) - ); -end repro_slv; - -architecture rtl of repro_slv is -begin - i_sub_slv : entity work.sub_slv - port map ( - clk => clk, - a => a, - b => b - ); -end rtl; diff --git a/testsuite/synth/issue34/repro_uns.vhdl b/testsuite/synth/issue34/repro_uns.vhdl deleted file mode 100644 index d0641d509..000000000 --- a/testsuite/synth/issue34/repro_uns.vhdl +++ /dev/null @@ -1,44 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity sub_uns is - port ( - clk : in std_logic; - a : in unsigned(7 downto 0); - b : out unsigned(7 downto 0) - ); -end sub_uns; - -architecture rtl of sub_uns is -begin - process(clk) - begin - if rising_edge(clk) then - b <= a; - end if; - end process; -end rtl; - - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity repro_uns is - port ( - clk : in std_logic; - a : in unsigned(7 downto 0); - b : out unsigned(7 downto 0) - ); -end repro_uns; - -architecture rtl of repro_uns is -begin - i_sub_uns : entity work.sub_uns - port map ( - clk => clk, - a => a, - b => b - ); -end rtl; diff --git a/testsuite/synth/issue34/submodule.vhdl b/testsuite/synth/issue34/submodule.vhdl deleted file mode 100644 index bc282985a..000000000 --- a/testsuite/synth/issue34/submodule.vhdl +++ /dev/null @@ -1,20 +0,0 @@ -library ieee; - use ieee.std_logic_1164.all; - -entity submodule is - port ( - clk : in std_logic; - a : in std_logic_vector(7 downto 0); - b : out std_logic_vector(7 downto 0) - ); -end submodule; - -architecture rtl of submodule is -begin - process(clk) - begin - if rising_edge(clk) then - b <= a; - end if; - end process; -end rtl; diff --git a/testsuite/synth/issue34/tb_repro_nat.vhdl b/testsuite/synth/issue34/tb_repro_nat.vhdl deleted file mode 100644 index acfe72fea..000000000 --- a/testsuite/synth/issue34/tb_repro_nat.vhdl +++ /dev/null @@ -1,34 +0,0 @@ -entity tb_repro_nat is -end tb_repro_nat; - -library ieee; -use ieee.std_logic_1164.all; - -architecture behav of tb_repro_nat is - signal clk : std_logic; - signal a : natural; - signal b : natural; -begin - dut: entity work.repro_nat - port map ( - clk => clk, a => a, b => b); - - process - procedure pulse is - begin - clk <= '0'; - wait for 1 ns; - clk <= '1'; - wait for 1 ns; - end pulse; - begin - a <= 125; - pulse; - assert b = 125 severity failure; - - a <= 7689; - pulse; - assert b = 7689 severity failure; - wait; - end process; -end behav; diff --git a/testsuite/synth/issue34/tb_repro_rng1.vhdl b/testsuite/synth/issue34/tb_repro_rng1.vhdl deleted file mode 100644 index 09f385a58..000000000 --- a/testsuite/synth/issue34/tb_repro_rng1.vhdl +++ /dev/null @@ -1,34 +0,0 @@ -entity tb_repro_rng1 is -end tb_repro_rng1; - -library ieee; -use ieee.std_logic_1164.all; - -architecture behav of tb_repro_rng1 is - signal clk : std_logic; - signal a : natural range 0 to 7; - signal b : natural range 0 to 7; -begin - dut: entity work.repro_rng1 - port map ( - clk => clk, a => a, b => b); - - process - procedure pulse is - begin - clk <= '0'; - wait for 1 ns; - clk <= '1'; - wait for 1 ns; - end pulse; - begin - a <= 1; - pulse; - assert b = 1 severity failure; - - a <= 6; - pulse; - assert b = 6 severity failure; - wait; - end process; -end behav; diff --git a/testsuite/synth/issue34/tb_repro_sgn.vhdl b/testsuite/synth/issue34/tb_repro_sgn.vhdl deleted file mode 100644 index 3961e6702..000000000 --- a/testsuite/synth/issue34/tb_repro_sgn.vhdl +++ /dev/null @@ -1,35 +0,0 @@ -entity tb_repro_sgn is -end tb_repro_sgn; - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -architecture behav of tb_repro_sgn is - signal clk : std_logic; - signal a : signed(7 downto 0); - signal b : signed(7 downto 0); -begin - dut: entity work.repro_sgn - port map ( - clk => clk, a => a, b => b); - - process - procedure pulse is - begin - clk <= '0'; - wait for 1 ns; - clk <= '1'; - wait for 1 ns; - end pulse; - begin - a <= x"ab"; - pulse; - assert b = x"ab" severity failure; - - a <= x"12"; - pulse; - assert b = x"12" severity failure; - wait; - end process; -end behav; diff --git a/testsuite/synth/issue34/tb_repro_slv.vhdl b/testsuite/synth/issue34/tb_repro_slv.vhdl deleted file mode 100644 index 45f0621eb..000000000 --- a/testsuite/synth/issue34/tb_repro_slv.vhdl +++ /dev/null @@ -1,34 +0,0 @@ -entity tb_repro_slv is -end tb_repro_slv; - -library ieee; -use ieee.std_logic_1164.all; - -architecture behav of tb_repro_slv is - signal clk : std_logic; - signal a : std_logic_vector(7 downto 0); - signal b : std_logic_vector(7 downto 0); -begin - dut: entity work.repro_slv - port map ( - clk => clk, a => a, b => b); - - process - procedure pulse is - begin - clk <= '0'; - wait for 1 ns; - clk <= '1'; - wait for 1 ns; - end pulse; - begin - a <= x"ab"; - pulse; - assert b = x"ab" severity failure; - - a <= x"12"; - pulse; - assert b = x"12" severity failure; - wait; - end process; -end behav; diff --git a/testsuite/synth/issue34/tb_repro_uns.vhdl b/testsuite/synth/issue34/tb_repro_uns.vhdl deleted file mode 100644 index a54a636eb..000000000 --- a/testsuite/synth/issue34/tb_repro_uns.vhdl +++ /dev/null @@ -1,35 +0,0 @@ -entity tb_repro_uns is -end tb_repro_uns; - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -architecture behav of tb_repro_uns is - signal clk : std_logic; - signal a : unsigned(7 downto 0); - signal b : unsigned(7 downto 0); -begin - dut: entity work.repro_uns - port map ( - clk => clk, a => a, b => b); - - process - procedure pulse is - begin - clk <= '0'; - wait for 1 ns; - clk <= '1'; - wait for 1 ns; - end pulse; - begin - a <= x"ab"; - pulse; - assert b = x"ab" severity failure; - - a <= x"12"; - pulse; - assert b = x"12" severity failure; - wait; - end process; -end behav; diff --git a/testsuite/synth/issue34/testsuite.sh b/testsuite/synth/issue34/testsuite.sh deleted file mode 100755 index 82088c6d8..000000000 --- a/testsuite/synth/issue34/testsuite.sh +++ /dev/null @@ -1,16 +0,0 @@ -#! /bin/sh - -. ../../testenv.sh - -for t in repro_slv repro_uns repro_sgn repro_nat repro_rng1; do - analyze $t.vhdl tb_$t.vhdl - elab_simulate tb_$t - clean - - synth $t.vhdl -e $t > syn_$t.vhdl - analyze syn_$t.vhdl tb_$t.vhdl - elab_simulate tb_$t - clean -done - -echo "Test successful" diff --git a/testsuite/synth/issue39/rec2.vhdl b/testsuite/synth/issue39/rec2.vhdl deleted file mode 100644 index a631d0505..000000000 --- a/testsuite/synth/issue39/rec2.vhdl +++ /dev/null @@ -1,43 +0,0 @@ -library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; - -entity rec2 is - port ( - clk : in std_logic; - - sl_in : in std_logic; - slv_in : in std_logic_vector(7 downto 0); - int_in : in integer range 0 to 15; - usig_in : in unsigned(7 downto 0); - - sl_out : out std_logic; - slv_out : out std_logic_vector(7 downto 0); - int_out : out integer range 0 to 15; - usig_out : out unsigned(7 downto 0) - ); -end rec2; - -architecture rtl of rec2 is - type t_record is record - sl : std_logic; - slv : std_logic_vector(7 downto 0); - int : integer range 0 to 15; - usig : unsigned(7 downto 0); - end record t_record; - signal sample_record : t_record; -begin - process(clk) - begin - if rising_edge(clk) then - sample_record.sl <= sl_in; - sample_record.slv <= slv_in; - sample_record.int <= int_in; - sample_record.usig <= usig_in; - end if; - end process; - sl_out <= sample_record.sl; - slv_out <= sample_record.slv; - int_out <= sample_record.int; - usig_out <= sample_record.usig; -end rtl; diff --git a/testsuite/synth/issue39/record_test.vhdl b/testsuite/synth/issue39/record_test.vhdl deleted file mode 100644 index b199cfa36..000000000 --- a/testsuite/synth/issue39/record_test.vhdl +++ /dev/null @@ -1,43 +0,0 @@ -library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; - -entity record_test is - port ( - clk : in std_logic; - - sl_in : in std_logic; - slv_in : in std_logic_vector(7 downto 0); - int_in : in integer range 0 to 15; - usig_in : in unsigned(7 downto 0); - - sl_out : out std_logic; - slv_out : out std_logic_vector(7 downto 0); - int_out : out integer range 0 to 15; - usig_out : out unsigned(7 downto 0) - ); -end record_test; - -architecture rtl of record_test is - type t_record is record - sl : std_logic; - slv : std_logic_vector(7 downto 0); - int : integer range 0 to 15; - usig : unsigned(7 downto 0); - end record t_record; - signal sample_record : t_record := ('0', (others => '0'), 0, (others => '0')); -begin - process(clk) - begin - if rising_edge(clk) then - sample_record.sl <= sl_in; - sample_record.slv <= slv_in; - sample_record.int <= int_in; - sample_record.usig <= usig_in; - end if; - end process; - sl_out <= sample_record.sl; - slv_out <= sample_record.slv; - int_out <= sample_record.int; - usig_out <= sample_record.usig; -end rtl; diff --git a/testsuite/synth/issue39/tb_rec2.vhdl b/testsuite/synth/issue39/tb_rec2.vhdl deleted file mode 100644 index 8d955df2d..000000000 --- a/testsuite/synth/issue39/tb_rec2.vhdl +++ /dev/null @@ -1,65 +0,0 @@ -entity tb_rec2 is -end tb_rec2; - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -architecture behav of tb_rec2 is - signal clk : std_logic; - signal sl_in : std_logic; - signal slv_in : std_logic_vector(7 downto 0); - signal int_in : integer range 0 to 15; - signal usig_in : unsigned(7 downto 0); - signal sl_out : std_logic; - signal slv_out : std_logic_vector(7 downto 0); - signal int_out : integer range 0 to 15; - signal usig_out : unsigned(7 downto 0); -begin - dut: entity work.rec2 - port map ( - clk => clk, - sl_in => sl_in, - slv_in => slv_in, - int_in => int_in, - usig_in => usig_in, - sl_out => sl_out, - slv_out => slv_out, - int_out => int_out, - usig_out => usig_out); - - process - begin - clk <= '0'; - sl_in <= '1'; - slv_in <= x"12"; - int_in <= 13; - usig_in <= x"d5"; - - wait for 1 ns; - clk <= '1'; - wait for 1 ns; - - assert sl_out = '1' severity failure; - assert slv_out = x"12" severity failure; - assert int_out = 13 severity failure; - assert usig_out = x"d5" severity failure; - - sl_in <= '0'; - slv_in <= x"9b"; - int_in <= 3; - usig_in <= x"72"; - - clk <= '0'; - wait for 1 ns; - clk <= '1'; - wait for 1 ns; - - assert sl_out = '0' severity failure; - assert slv_out = x"9b" severity failure; - assert int_out = 3 severity failure; - assert usig_out = x"72" severity failure; - - wait; - end process; -end behav; diff --git a/testsuite/synth/issue39/tb_record_test.vhdl b/testsuite/synth/issue39/tb_record_test.vhdl deleted file mode 100644 index 31db03d59..000000000 --- a/testsuite/synth/issue39/tb_record_test.vhdl +++ /dev/null @@ -1,65 +0,0 @@ -entity tb_record_test is -end tb_record_test; - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -architecture behav of tb_record_test is - signal clk : std_logic; - signal sl_in : std_logic; - signal slv_in : std_logic_vector(7 downto 0); - signal int_in : integer range 0 to 15; - signal usig_in : unsigned(7 downto 0); - signal sl_out : std_logic; - signal slv_out : std_logic_vector(7 downto 0); - signal int_out : integer range 0 to 15; - signal usig_out : unsigned(7 downto 0); -begin - dut: entity work.record_test - port map ( - clk => clk, - sl_in => sl_in, - slv_in => slv_in, - int_in => int_in, - usig_in => usig_in, - sl_out => sl_out, - slv_out => slv_out, - int_out => int_out, - usig_out => usig_out); - - process - begin - clk <= '0'; - sl_in <= '1'; - slv_in <= x"12"; - int_in <= 13; - usig_in <= x"d5"; - - wait for 1 ns; - clk <= '1'; - wait for 1 ns; - - assert sl_out = '1' severity failure; - assert slv_out = x"12" severity failure; - assert int_out = 13 severity failure; - assert usig_out = x"d5" severity failure; - - sl_in <= '0'; - slv_in <= x"9b"; - int_in <= 3; - usig_in <= x"72"; - - clk <= '0'; - wait for 1 ns; - clk <= '1'; - wait for 1 ns; - - assert sl_out = '0' severity failure; - assert slv_out = x"9b" severity failure; - assert int_out = 3 severity failure; - assert usig_out = x"72" severity failure; - - wait; - end process; -end behav; diff --git a/testsuite/synth/issue39/testsuite.sh b/testsuite/synth/issue39/testsuite.sh deleted file mode 100755 index 9bef83a1f..000000000 --- a/testsuite/synth/issue39/testsuite.sh +++ /dev/null @@ -1,16 +0,0 @@ -#! /bin/sh - -. ../../testenv.sh - -for t in record_test rec2; do - analyze $t.vhdl tb_$t.vhdl - elab_simulate tb_$t - clean - - synth $t.vhdl -e $t > syn_$t.vhdl - analyze syn_$t.vhdl tb_$t.vhdl - elab_simulate tb_$t - clean -done - -echo "Test successful" diff --git a/testsuite/synth/issue40/tb_testcase.vhdl b/testsuite/synth/issue40/tb_testcase.vhdl deleted file mode 100644 index 3ed89e61c..000000000 --- a/testsuite/synth/issue40/tb_testcase.vhdl +++ /dev/null @@ -1,26 +0,0 @@ -entity tb_testcase is -end tb_testcase; - -library ieee; -use ieee.std_logic_1164.all; - -architecture behav of tb_testcase is - signal di : std_logic; - signal do : std_logic; -begin - dut: entity work.testcase - port map (data_in => di, data_out => do); - - process - begin - di <= '1'; - wait for 1 ns; - assert do = '0' severity failure; - - di <= '0'; - wait for 1 ns; - assert do = '1' severity failure; - - wait; - end process; -end behav; diff --git a/testsuite/synth/issue40/testcase.vhdl b/testsuite/synth/issue40/testcase.vhdl deleted file mode 100644 index 8055fac85..000000000 --- a/testsuite/synth/issue40/testcase.vhdl +++ /dev/null @@ -1,17 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; - -entity testcase is - port( - data_in : in std_ulogic; - data_out : out std_ulogic - ); -end entity testcase; - -architecture behaviour of testcase is -begin - comb : process(all) - begin - data_out <= '1' when data_in = '0' else '0'; - end process; -end architecture behaviour; diff --git a/testsuite/synth/issue40/testsuite.sh b/testsuite/synth/issue40/testsuite.sh deleted file mode 100755 index 54d4ea0ed..000000000 --- a/testsuite/synth/issue40/testsuite.sh +++ /dev/null @@ -1,18 +0,0 @@ -#! /bin/sh - -. ../../testenv.sh - -GHDL_STD_FLAGS=--std=08 - -for t in testcase; do - analyze $t.vhdl tb_$t.vhdl - elab_simulate tb_$t - clean - - synth $t.vhdl -e $t > syn_$t.vhdl - analyze syn_$t.vhdl tb_$t.vhdl - elab_simulate tb_$t - clean -done - -echo "Test successful" diff --git a/testsuite/synth/issue8/tb_test5.vhdl b/testsuite/synth/issue8/tb_test5.vhdl deleted file mode 100644 index 14ef0660e..000000000 --- a/testsuite/synth/issue8/tb_test5.vhdl +++ /dev/null @@ -1,19 +0,0 @@ -entity tb_test5 is -end tb_test5; - -library ieee; -use ieee.std_logic_1164.all; - -architecture behav of tb_test5 is - signal r : std_logic_vector(7 downto 0); -begin - dut: entity work.test5 - port map (r); - - process - begin - wait for 1 ns; - assert r(7) = '1' severity failure; - wait; - end process; -end behav; diff --git a/testsuite/synth/issue8/tb_vector8_test1.vhdl b/testsuite/synth/issue8/tb_vector8_test1.vhdl deleted file mode 100644 index 0a37884d5..000000000 --- a/testsuite/synth/issue8/tb_vector8_test1.vhdl +++ /dev/null @@ -1,19 +0,0 @@ -entity tb_vector8_test1 is -end tb_vector8_test1; - -library ieee; -use ieee.std_logic_1164.all; - -architecture behav of tb_vector8_test1 is - signal r : std_logic; -begin - dut: entity work.vector8_test1 - port map (r); - - process - begin - wait for 1 ns; - assert r = '1' severity failure; - wait; - end process; -end behav; diff --git a/testsuite/synth/issue8/test2.vhdl b/testsuite/synth/issue8/test2.vhdl deleted file mode 100644 index dca1601bb..000000000 --- a/testsuite/synth/issue8/test2.vhdl +++ /dev/null @@ -1,15 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; - -entity test2 is - port (led: out std_logic_vector (7 downto 0)); -end test2; - -architecture synth of test2 is - -begin - led(7) <= '0'; - led(6) <= '1'; --- led(5) <= '0'; --- led(3 downto 0) <= x"9"; -end synth; diff --git a/testsuite/synth/issue8/test3.vhdl b/testsuite/synth/issue8/test3.vhdl deleted file mode 100644 index 3e17936ca..000000000 --- a/testsuite/synth/issue8/test3.vhdl +++ /dev/null @@ -1,28 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; - -entity test3 is - port (led: out std_logic_vector (7 downto 0); - rst : std_logic; - clk : std_logic); -end test3; - -architecture synth of test3 is - signal int : std_logic_vector(1 downto 0); -begin --- led(7) <= '0'; --- led(6) <= '1'; --- led(5) <= '0'; --- led(3 downto 0) <= x"9"; - process (clk) is - begin - if rising_edge (clk) then - if rst = '1' then - int(1) <= '0'; - else - int(1) <= not int(1); - end if; - end if; - end process; - led(5) <= int (1); -end synth; diff --git a/testsuite/synth/issue8/test4.vhdl b/testsuite/synth/issue8/test4.vhdl deleted file mode 100644 index 4875fa1ec..000000000 --- a/testsuite/synth/issue8/test4.vhdl +++ /dev/null @@ -1,28 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; - -entity test4 is - port (led: out std_logic_vector (7 downto 0); - rst : std_logic; - clk : std_logic); -end test4; - -architecture synth of test4 is - signal int : std_logic_vector(1 downto 0); -begin --- led(7) <= '0'; --- led(6) <= '1'; --- led(5) <= '0'; --- led(3 downto 0) <= x"9"; --- int(0) <= '0'; - process (clk) is - begin - if rst = '1' then - int(1) <= '0'; - elsif rising_edge (clk) then - int(1) <= not int(1); - end if; - end process; - led(5) <= int (1); --- led(4) <= int(0); -end synth; diff --git a/testsuite/synth/issue8/test5.vhdl b/testsuite/synth/issue8/test5.vhdl deleted file mode 100644 index 0d1fbc0e5..000000000 --- a/testsuite/synth/issue8/test5.vhdl +++ /dev/null @@ -1,15 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; - -entity test5 is - port (led: out std_logic_vector (7 downto 0)); -end test5; - -architecture synth of test5 is - -begin - led(7) <= '1'; --- led(6) <= '1'; --- led(5) <= '0'; --- led(3 downto 0) <= x"9"; -end synth; diff --git a/testsuite/synth/issue8/testsuite.sh b/testsuite/synth/issue8/testsuite.sh deleted file mode 100755 index df039cb08..000000000 --- a/testsuite/synth/issue8/testsuite.sh +++ /dev/null @@ -1,16 +0,0 @@ -#! /bin/sh - -. ../../testenv.sh - -for t in vector8_test1 test5; do - analyze $t.vhdl tb_$t.vhdl - elab_simulate tb_$t - clean - - synth $t.vhdl -e $t > syn_$t.vhdl - analyze syn_$t.vhdl tb_$t.vhdl - elab_simulate tb_$t - clean -done - -echo "Test successful" diff --git a/testsuite/synth/issue8/vector8_test1.vhdl b/testsuite/synth/issue8/vector8_test1.vhdl deleted file mode 100644 index 585d003b0..000000000 --- a/testsuite/synth/issue8/vector8_test1.vhdl +++ /dev/null @@ -1,16 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity vector8_test1 is - port (led7: out std_logic); -end vector8_test1; - -architecture synth of vector8_test1 is - -signal v : std_logic_vector(7 downto 0); - -begin - v(7) <= '1'; - led7 <= v(7); -end synth; diff --git a/testsuite/synth/synth12/lut.vhdl b/testsuite/synth/synth12/lut.vhdl new file mode 100644 index 000000000..5c04e8d9a --- /dev/null +++ b/testsuite/synth/synth12/lut.vhdl @@ -0,0 +1,25 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity lut is port ( + sel: in std_logic_vector (1 downto 0); + c: out std_logic); +end lut; + +-- sel(1) sel(0) | c +-- 0 0 | 1 +-- 0 1 | 0 +-- 1 0 | 1 +-- 1 1 | 0 + +architecture synth of lut is +begin + +with sel select c <= + + '1' when "00", + '0' when "01", + '1' when "10", + '0' when others; + +end synth; diff --git a/testsuite/synth/synth12/tb_lut.vhdl b/testsuite/synth/synth12/tb_lut.vhdl new file mode 100644 index 000000000..f8f5cf3a6 --- /dev/null +++ b/testsuite/synth/synth12/tb_lut.vhdl @@ -0,0 +1,34 @@ +entity tb_lut is +end tb_lut; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_lut is + signal c : std_logic; + signal s : std_logic_vector(1 downto 0); +begin + dut: entity work.lut + port map (s, c); + + process + begin + s <= "00"; + wait for 1 ns; + assert c = '1' severity failure; + + s <= "01"; + wait for 1 ns; + assert c = '0' severity failure; + + s <= "10"; + wait for 1 ns; + assert c = '1' severity failure; + + s <= "11"; + wait for 1 ns; + assert c = '0' severity failure; + + wait; + end process; +end behav; diff --git a/testsuite/synth/synth12/testsuite.sh b/testsuite/synth/synth12/testsuite.sh new file mode 100755 index 000000000..a65695152 --- /dev/null +++ b/testsuite/synth/synth12/testsuite.sh @@ -0,0 +1,16 @@ +#! /bin/sh + +. ../../testenv.sh + +for t in lut; do + analyze $t.vhdl tb_$t.vhdl + elab_simulate tb_$t + clean + + synth $t.vhdl -e $t > syn_$t.vhdl + analyze syn_$t.vhdl tb_$t.vhdl + elab_simulate tb_$t + clean +done + +echo "Test successful" diff --git a/testsuite/synth/synth26/int_test.vhdl b/testsuite/synth/synth26/int_test.vhdl new file mode 100644 index 000000000..afc8c4cdb --- /dev/null +++ b/testsuite/synth/synth26/int_test.vhdl @@ -0,0 +1,20 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity int_test is + port (clk : in std_logic; + a, b : in integer range 0 to 1; + c : out std_logic); +end int_test; + +architecture rtl of int_test is +begin + process (clk) + begin + if rising_edge (clk) then + if a < b then + c <= '0'; + end if; + end if; + end process; +end rtl; diff --git a/testsuite/synth/synth26/testsuite.sh b/testsuite/synth/synth26/testsuite.sh new file mode 100755 index 000000000..1cc0536d7 --- /dev/null +++ b/testsuite/synth/synth26/testsuite.sh @@ -0,0 +1,9 @@ +#! /bin/sh + +. ../../testenv.sh + +synth int_test.vhdl -e int_test > syn_int_test.vhdl +analyze syn_int_test.vhdl +clean + +echo "Test successful" diff --git a/testsuite/synth/synth27/dff.vhdl b/testsuite/synth/synth27/dff.vhdl new file mode 100644 index 000000000..2bf3ebec8 --- /dev/null +++ b/testsuite/synth/synth27/dff.vhdl @@ -0,0 +1,40 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity dff is + generic( + formal_g : boolean := true + ); + port( + reset : in std_logic; + clk : in std_logic; + d : in std_logic; + q : out std_logic + ); +end entity dff; + +architecture rtl of dff is + signal q_int : std_logic; +begin + + dff_proc : process(clk, reset) + begin + if reset = '1' then + q_int <= '0'; + elsif rising_edge(clk) then + q_int <= d; + end if; + end process dff_proc; + + -- drive q_int to output port + q <= q_int; + + formal_gen : if formal_g = true generate + begin + -- set all declarations to run on clk + default clock is rising_edge(clk); + d_in_check : assert always {d} |=> {q_int}; + not_d_in_check : assert always {not d} |=> {not q_int}; + end generate formal_gen; + +end rtl; diff --git a/testsuite/synth/synth27/testsuite.sh b/testsuite/synth/synth27/testsuite.sh new file mode 100755 index 000000000..b5ed1a2b7 --- /dev/null +++ b/testsuite/synth/synth27/testsuite.sh @@ -0,0 +1,8 @@ +#! /bin/sh + +. ../../testenv.sh + +export GHDL_STD_FLAGS=--std=08 +synth dff.vhdl -e dff > syn_dff.vhdl + +echo "Test successful" diff --git a/testsuite/synth/synth33/int_test.vhdl b/testsuite/synth/synth33/int_test.vhdl new file mode 100644 index 000000000..62ea65bda --- /dev/null +++ b/testsuite/synth/synth33/int_test.vhdl @@ -0,0 +1,31 @@ +library ieee; + use ieee.std_logic_1164.all; + +entity int_test is + generic ( + INT_MIN : integer range 1 to 8 := 1; + INT_MAX : integer range 1 to 8 := 8 + ); + port ( + clk : in std_logic; + a : in integer range INT_MIN to INT_MAX; + b : out integer range INT_MIN to INT_MAX + ); +end int_test; + +architecture rtl of int_test is + signal int : integer range INT_MIN to INT_MAX; +begin + process (clk) + begin + if rising_edge (clk) then + if a < INT_MAX then + int <= a + 1; + else + int <= INT_MIN; + end if; + end if; + end process; + b <= int; +end rtl; + diff --git a/testsuite/synth/synth33/int_test2.vhdl b/testsuite/synth/synth33/int_test2.vhdl new file mode 100644 index 000000000..eb43306c4 --- /dev/null +++ b/testsuite/synth/synth33/int_test2.vhdl @@ -0,0 +1,31 @@ +library ieee; + use ieee.std_logic_1164.all; + +entity int_test2 is + generic ( + INT_MIN : integer range 1 to 8 := 1; + INT_MAX : integer range 1 to 8 := 8 + ); + port ( + clk : in std_logic; + a : in integer range INT_MIN to INT_MAX; + b : out integer range INT_MIN to INT_MAX + ); +end int_test2; + +architecture rtl of int_test2 is + signal int : integer range INT_MIN to INT_MAX; +begin + process (clk) + begin + if rising_edge (clk) then + if a < INT_MAX then + int <= a + 1; + else + int <= INT_MIN * 2; + end if; + end if; + end process; + b <= int; +end rtl; + diff --git a/testsuite/synth/synth33/testsuite.sh b/testsuite/synth/synth33/testsuite.sh new file mode 100755 index 000000000..fca6f7d69 --- /dev/null +++ b/testsuite/synth/synth33/testsuite.sh @@ -0,0 +1,11 @@ +#! /bin/sh + +. ../../testenv.sh + +for t in int_test int_test2; do + synth $t.vhdl -e $t > syn_$t.vhdl + analyze syn_$t.vhdl + clean +done + +echo "Test successful" diff --git a/testsuite/synth/synth34/module.vhdl b/testsuite/synth/synth34/module.vhdl new file mode 100644 index 000000000..67f3dd4b3 --- /dev/null +++ b/testsuite/synth/synth34/module.vhdl @@ -0,0 +1,20 @@ +library ieee; + use ieee.std_logic_1164.all; + +entity module is + port ( + clk : in std_logic; + a : in std_logic_vector(7 downto 0); + b : out std_logic_vector(7 downto 0) + ); +end module; + +architecture rtl of module is +begin + i_submodule : entity work.submodule + port map ( + clk => clk, + a => a, + b => b + ); +end rtl; diff --git a/testsuite/synth/synth34/repro_nat.vhdl b/testsuite/synth/synth34/repro_nat.vhdl new file mode 100644 index 000000000..328c11781 --- /dev/null +++ b/testsuite/synth/synth34/repro_nat.vhdl @@ -0,0 +1,42 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity sub_nat is + port ( + clk : in std_logic; + a : in natural; + b : out natural + ); +end sub_nat; + +architecture rtl of sub_nat is +begin + process(clk) + begin + if rising_edge(clk) then + b <= a; + end if; + end process; +end rtl; + + +library ieee; +use ieee.std_logic_1164.all; + +entity repro_nat is + port ( + clk : in std_logic; + a : in natural; + b : out natural + ); +end repro_nat; + +architecture rtl of repro_nat is +begin + i_sub_nat : entity work.sub_nat + port map ( + clk => clk, + a => a, + b => b + ); +end rtl; diff --git a/testsuite/synth/synth34/repro_rng1.vhdl b/testsuite/synth/synth34/repro_rng1.vhdl new file mode 100644 index 000000000..9d5a70e04 --- /dev/null +++ b/testsuite/synth/synth34/repro_rng1.vhdl @@ -0,0 +1,42 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity sub_rng1 is + port ( + clk : in std_logic; + a : in natural range 0 to 7; + b : out natural range 0 to 7 + ); +end sub_rng1; + +architecture rtl of sub_rng1 is +begin + process(clk) + begin + if rising_edge(clk) then + b <= a; + end if; + end process; +end rtl; + + +library ieee; +use ieee.std_logic_1164.all; + +entity repro_rng1 is + port ( + clk : in std_logic; + a : in natural range 0 to 7; + b : out natural range 0 to 7 + ); +end repro_rng1; + +architecture rtl of repro_rng1 is +begin + i_sub_rng1 : entity work.sub_rng1 + port map ( + clk => clk, + a => a, + b => b + ); +end rtl; diff --git a/testsuite/synth/synth34/repro_sgn.vhdl b/testsuite/synth/synth34/repro_sgn.vhdl new file mode 100644 index 000000000..fa23693d3 --- /dev/null +++ b/testsuite/synth/synth34/repro_sgn.vhdl @@ -0,0 +1,44 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity sub_sgn is + port ( + clk : in std_logic; + a : in signed(7 downto 0); + b : out signed(7 downto 0) + ); +end sub_sgn; + +architecture rtl of sub_sgn is +begin + process(clk) + begin + if rising_edge(clk) then + b <= a; + end if; + end process; +end rtl; + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity repro_sgn is + port ( + clk : in std_logic; + a : in signed(7 downto 0); + b : out signed(7 downto 0) + ); +end repro_sgn; + +architecture rtl of repro_sgn is +begin + i_sub_sgn : entity work.sub_sgn + port map ( + clk => clk, + a => a, + b => b + ); +end rtl; diff --git a/testsuite/synth/synth34/repro_slv.vhdl b/testsuite/synth/synth34/repro_slv.vhdl new file mode 100644 index 000000000..4b0e1b0e5 --- /dev/null +++ b/testsuite/synth/synth34/repro_slv.vhdl @@ -0,0 +1,42 @@ +library ieee; + use ieee.std_logic_1164.all; + +entity sub_slv is + port ( + clk : in std_logic; + a : in std_logic_vector(7 downto 0); + b : out std_logic_vector(7 downto 0) + ); +end sub_slv; + +architecture rtl of sub_slv is +begin + process(clk) + begin + if rising_edge(clk) then + b <= a; + end if; + end process; +end rtl; + + +library ieee; + use ieee.std_logic_1164.all; + +entity repro_slv is + port ( + clk : in std_logic; + a : in std_logic_vector(7 downto 0); + b : out std_logic_vector(7 downto 0) + ); +end repro_slv; + +architecture rtl of repro_slv is +begin + i_sub_slv : entity work.sub_slv + port map ( + clk => clk, + a => a, + b => b + ); +end rtl; diff --git a/testsuite/synth/synth34/repro_uns.vhdl b/testsuite/synth/synth34/repro_uns.vhdl new file mode 100644 index 000000000..d0641d509 --- /dev/null +++ b/testsuite/synth/synth34/repro_uns.vhdl @@ -0,0 +1,44 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity sub_uns is + port ( + clk : in std_logic; + a : in unsigned(7 downto 0); + b : out unsigned(7 downto 0) + ); +end sub_uns; + +architecture rtl of sub_uns is +begin + process(clk) + begin + if rising_edge(clk) then + b <= a; + end if; + end process; +end rtl; + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity repro_uns is + port ( + clk : in std_logic; + a : in unsigned(7 downto 0); + b : out unsigned(7 downto 0) + ); +end repro_uns; + +architecture rtl of repro_uns is +begin + i_sub_uns : entity work.sub_uns + port map ( + clk => clk, + a => a, + b => b + ); +end rtl; diff --git a/testsuite/synth/synth34/submodule.vhdl b/testsuite/synth/synth34/submodule.vhdl new file mode 100644 index 000000000..bc282985a --- /dev/null +++ b/testsuite/synth/synth34/submodule.vhdl @@ -0,0 +1,20 @@ +library ieee; + use ieee.std_logic_1164.all; + +entity submodule is + port ( + clk : in std_logic; + a : in std_logic_vector(7 downto 0); + b : out std_logic_vector(7 downto 0) + ); +end submodule; + +architecture rtl of submodule is +begin + process(clk) + begin + if rising_edge(clk) then + b <= a; + end if; + end process; +end rtl; diff --git a/testsuite/synth/synth34/tb_repro_nat.vhdl b/testsuite/synth/synth34/tb_repro_nat.vhdl new file mode 100644 index 000000000..acfe72fea --- /dev/null +++ b/testsuite/synth/synth34/tb_repro_nat.vhdl @@ -0,0 +1,34 @@ +entity tb_repro_nat is +end tb_repro_nat; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_repro_nat is + signal clk : std_logic; + signal a : natural; + signal b : natural; +begin + dut: entity work.repro_nat + port map ( + clk => clk, a => a, b => b); + + process + procedure pulse is + begin + clk <= '0'; + wait for 1 ns; + clk <= '1'; + wait for 1 ns; + end pulse; + begin + a <= 125; + pulse; + assert b = 125 severity failure; + + a <= 7689; + pulse; + assert b = 7689 severity failure; + wait; + end process; +end behav; diff --git a/testsuite/synth/synth34/tb_repro_rng1.vhdl b/testsuite/synth/synth34/tb_repro_rng1.vhdl new file mode 100644 index 000000000..09f385a58 --- /dev/null +++ b/testsuite/synth/synth34/tb_repro_rng1.vhdl @@ -0,0 +1,34 @@ +entity tb_repro_rng1 is +end tb_repro_rng1; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_repro_rng1 is + signal clk : std_logic; + signal a : natural range 0 to 7; + signal b : natural range 0 to 7; +begin + dut: entity work.repro_rng1 + port map ( + clk => clk, a => a, b => b); + + process + procedure pulse is + begin + clk <= '0'; + wait for 1 ns; + clk <= '1'; + wait for 1 ns; + end pulse; + begin + a <= 1; + pulse; + assert b = 1 severity failure; + + a <= 6; + pulse; + assert b = 6 severity failure; + wait; + end process; +end behav; diff --git a/testsuite/synth/synth34/tb_repro_sgn.vhdl b/testsuite/synth/synth34/tb_repro_sgn.vhdl new file mode 100644 index 000000000..3961e6702 --- /dev/null +++ b/testsuite/synth/synth34/tb_repro_sgn.vhdl @@ -0,0 +1,35 @@ +entity tb_repro_sgn is +end tb_repro_sgn; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +architecture behav of tb_repro_sgn is + signal clk : std_logic; + signal a : signed(7 downto 0); + signal b : signed(7 downto 0); +begin + dut: entity work.repro_sgn + port map ( + clk => clk, a => a, b => b); + + process + procedure pulse is + begin + clk <= '0'; + wait for 1 ns; + clk <= '1'; + wait for 1 ns; + end pulse; + begin + a <= x"ab"; + pulse; + assert b = x"ab" severity failure; + + a <= x"12"; + pulse; + assert b = x"12" severity failure; + wait; + end process; +end behav; diff --git a/testsuite/synth/synth34/tb_repro_slv.vhdl b/testsuite/synth/synth34/tb_repro_slv.vhdl new file mode 100644 index 000000000..45f0621eb --- /dev/null +++ b/testsuite/synth/synth34/tb_repro_slv.vhdl @@ -0,0 +1,34 @@ +entity tb_repro_slv is +end tb_repro_slv; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_repro_slv is + signal clk : std_logic; + signal a : std_logic_vector(7 downto 0); + signal b : std_logic_vector(7 downto 0); +begin + dut: entity work.repro_slv + port map ( + clk => clk, a => a, b => b); + + process + procedure pulse is + begin + clk <= '0'; + wait for 1 ns; + clk <= '1'; + wait for 1 ns; + end pulse; + begin + a <= x"ab"; + pulse; + assert b = x"ab" severity failure; + + a <= x"12"; + pulse; + assert b = x"12" severity failure; + wait; + end process; +end behav; diff --git a/testsuite/synth/synth34/tb_repro_uns.vhdl b/testsuite/synth/synth34/tb_repro_uns.vhdl new file mode 100644 index 000000000..a54a636eb --- /dev/null +++ b/testsuite/synth/synth34/tb_repro_uns.vhdl @@ -0,0 +1,35 @@ +entity tb_repro_uns is +end tb_repro_uns; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +architecture behav of tb_repro_uns is + signal clk : std_logic; + signal a : unsigned(7 downto 0); + signal b : unsigned(7 downto 0); +begin + dut: entity work.repro_uns + port map ( + clk => clk, a => a, b => b); + + process + procedure pulse is + begin + clk <= '0'; + wait for 1 ns; + clk <= '1'; + wait for 1 ns; + end pulse; + begin + a <= x"ab"; + pulse; + assert b = x"ab" severity failure; + + a <= x"12"; + pulse; + assert b = x"12" severity failure; + wait; + end process; +end behav; diff --git a/testsuite/synth/synth34/testsuite.sh b/testsuite/synth/synth34/testsuite.sh new file mode 100755 index 000000000..82088c6d8 --- /dev/null +++ b/testsuite/synth/synth34/testsuite.sh @@ -0,0 +1,16 @@ +#! /bin/sh + +. ../../testenv.sh + +for t in repro_slv repro_uns repro_sgn repro_nat repro_rng1; do + analyze $t.vhdl tb_$t.vhdl + elab_simulate tb_$t + clean + + synth $t.vhdl -e $t > syn_$t.vhdl + analyze syn_$t.vhdl tb_$t.vhdl + elab_simulate tb_$t + clean +done + +echo "Test successful" diff --git a/testsuite/synth/synth39/rec2.vhdl b/testsuite/synth/synth39/rec2.vhdl new file mode 100644 index 000000000..a631d0505 --- /dev/null +++ b/testsuite/synth/synth39/rec2.vhdl @@ -0,0 +1,43 @@ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity rec2 is + port ( + clk : in std_logic; + + sl_in : in std_logic; + slv_in : in std_logic_vector(7 downto 0); + int_in : in integer range 0 to 15; + usig_in : in unsigned(7 downto 0); + + sl_out : out std_logic; + slv_out : out std_logic_vector(7 downto 0); + int_out : out integer range 0 to 15; + usig_out : out unsigned(7 downto 0) + ); +end rec2; + +architecture rtl of rec2 is + type t_record is record + sl : std_logic; + slv : std_logic_vector(7 downto 0); + int : integer range 0 to 15; + usig : unsigned(7 downto 0); + end record t_record; + signal sample_record : t_record; +begin + process(clk) + begin + if rising_edge(clk) then + sample_record.sl <= sl_in; + sample_record.slv <= slv_in; + sample_record.int <= int_in; + sample_record.usig <= usig_in; + end if; + end process; + sl_out <= sample_record.sl; + slv_out <= sample_record.slv; + int_out <= sample_record.int; + usig_out <= sample_record.usig; +end rtl; diff --git a/testsuite/synth/synth39/record_test.vhdl b/testsuite/synth/synth39/record_test.vhdl new file mode 100644 index 000000000..b199cfa36 --- /dev/null +++ b/testsuite/synth/synth39/record_test.vhdl @@ -0,0 +1,43 @@ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity record_test is + port ( + clk : in std_logic; + + sl_in : in std_logic; + slv_in : in std_logic_vector(7 downto 0); + int_in : in integer range 0 to 15; + usig_in : in unsigned(7 downto 0); + + sl_out : out std_logic; + slv_out : out std_logic_vector(7 downto 0); + int_out : out integer range 0 to 15; + usig_out : out unsigned(7 downto 0) + ); +end record_test; + +architecture rtl of record_test is + type t_record is record + sl : std_logic; + slv : std_logic_vector(7 downto 0); + int : integer range 0 to 15; + usig : unsigned(7 downto 0); + end record t_record; + signal sample_record : t_record := ('0', (others => '0'), 0, (others => '0')); +begin + process(clk) + begin + if rising_edge(clk) then + sample_record.sl <= sl_in; + sample_record.slv <= slv_in; + sample_record.int <= int_in; + sample_record.usig <= usig_in; + end if; + end process; + sl_out <= sample_record.sl; + slv_out <= sample_record.slv; + int_out <= sample_record.int; + usig_out <= sample_record.usig; +end rtl; diff --git a/testsuite/synth/synth39/tb_rec2.vhdl b/testsuite/synth/synth39/tb_rec2.vhdl new file mode 100644 index 000000000..8d955df2d --- /dev/null +++ b/testsuite/synth/synth39/tb_rec2.vhdl @@ -0,0 +1,65 @@ +entity tb_rec2 is +end tb_rec2; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +architecture behav of tb_rec2 is + signal clk : std_logic; + signal sl_in : std_logic; + signal slv_in : std_logic_vector(7 downto 0); + signal int_in : integer range 0 to 15; + signal usig_in : unsigned(7 downto 0); + signal sl_out : std_logic; + signal slv_out : std_logic_vector(7 downto 0); + signal int_out : integer range 0 to 15; + signal usig_out : unsigned(7 downto 0); +begin + dut: entity work.rec2 + port map ( + clk => clk, + sl_in => sl_in, + slv_in => slv_in, + int_in => int_in, + usig_in => usig_in, + sl_out => sl_out, + slv_out => slv_out, + int_out => int_out, + usig_out => usig_out); + + process + begin + clk <= '0'; + sl_in <= '1'; + slv_in <= x"12"; + int_in <= 13; + usig_in <= x"d5"; + + wait for 1 ns; + clk <= '1'; + wait for 1 ns; + + assert sl_out = '1' severity failure; + assert slv_out = x"12" severity failure; + assert int_out = 13 severity failure; + assert usig_out = x"d5" severity failure; + + sl_in <= '0'; + slv_in <= x"9b"; + int_in <= 3; + usig_in <= x"72"; + + clk <= '0'; + wait for 1 ns; + clk <= '1'; + wait for 1 ns; + + assert sl_out = '0' severity failure; + assert slv_out = x"9b" severity failure; + assert int_out = 3 severity failure; + assert usig_out = x"72" severity failure; + + wait; + end process; +end behav; diff --git a/testsuite/synth/synth39/tb_record_test.vhdl b/testsuite/synth/synth39/tb_record_test.vhdl new file mode 100644 index 000000000..31db03d59 --- /dev/null +++ b/testsuite/synth/synth39/tb_record_test.vhdl @@ -0,0 +1,65 @@ +entity tb_record_test is +end tb_record_test; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +architecture behav of tb_record_test is + signal clk : std_logic; + signal sl_in : std_logic; + signal slv_in : std_logic_vector(7 downto 0); + signal int_in : integer range 0 to 15; + signal usig_in : unsigned(7 downto 0); + signal sl_out : std_logic; + signal slv_out : std_logic_vector(7 downto 0); + signal int_out : integer range 0 to 15; + signal usig_out : unsigned(7 downto 0); +begin + dut: entity work.record_test + port map ( + clk => clk, + sl_in => sl_in, + slv_in => slv_in, + int_in => int_in, + usig_in => usig_in, + sl_out => sl_out, + slv_out => slv_out, + int_out => int_out, + usig_out => usig_out); + + process + begin + clk <= '0'; + sl_in <= '1'; + slv_in <= x"12"; + int_in <= 13; + usig_in <= x"d5"; + + wait for 1 ns; + clk <= '1'; + wait for 1 ns; + + assert sl_out = '1' severity failure; + assert slv_out = x"12" severity failure; + assert int_out = 13 severity failure; + assert usig_out = x"d5" severity failure; + + sl_in <= '0'; + slv_in <= x"9b"; + int_in <= 3; + usig_in <= x"72"; + + clk <= '0'; + wait for 1 ns; + clk <= '1'; + wait for 1 ns; + + assert sl_out = '0' severity failure; + assert slv_out = x"9b" severity failure; + assert int_out = 3 severity failure; + assert usig_out = x"72" severity failure; + + wait; + end process; +end behav; diff --git a/testsuite/synth/synth39/testsuite.sh b/testsuite/synth/synth39/testsuite.sh new file mode 100755 index 000000000..9bef83a1f --- /dev/null +++ b/testsuite/synth/synth39/testsuite.sh @@ -0,0 +1,16 @@ +#! /bin/sh + +. ../../testenv.sh + +for t in record_test rec2; do + analyze $t.vhdl tb_$t.vhdl + elab_simulate tb_$t + clean + + synth $t.vhdl -e $t > syn_$t.vhdl + analyze syn_$t.vhdl tb_$t.vhdl + elab_simulate tb_$t + clean +done + +echo "Test successful" diff --git a/testsuite/synth/synth40/tb_testcase.vhdl b/testsuite/synth/synth40/tb_testcase.vhdl new file mode 100644 index 000000000..3ed89e61c --- /dev/null +++ b/testsuite/synth/synth40/tb_testcase.vhdl @@ -0,0 +1,26 @@ +entity tb_testcase is +end tb_testcase; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_testcase is + signal di : std_logic; + signal do : std_logic; +begin + dut: entity work.testcase + port map (data_in => di, data_out => do); + + process + begin + di <= '1'; + wait for 1 ns; + assert do = '0' severity failure; + + di <= '0'; + wait for 1 ns; + assert do = '1' severity failure; + + wait; + end process; +end behav; diff --git a/testsuite/synth/synth40/testcase.vhdl b/testsuite/synth/synth40/testcase.vhdl new file mode 100644 index 000000000..8055fac85 --- /dev/null +++ b/testsuite/synth/synth40/testcase.vhdl @@ -0,0 +1,17 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity testcase is + port( + data_in : in std_ulogic; + data_out : out std_ulogic + ); +end entity testcase; + +architecture behaviour of testcase is +begin + comb : process(all) + begin + data_out <= '1' when data_in = '0' else '0'; + end process; +end architecture behaviour; diff --git a/testsuite/synth/synth40/testsuite.sh b/testsuite/synth/synth40/testsuite.sh new file mode 100755 index 000000000..54d4ea0ed --- /dev/null +++ b/testsuite/synth/synth40/testsuite.sh @@ -0,0 +1,18 @@ +#! /bin/sh + +. ../../testenv.sh + +GHDL_STD_FLAGS=--std=08 + +for t in testcase; do + analyze $t.vhdl tb_$t.vhdl + elab_simulate tb_$t + clean + + synth $t.vhdl -e $t > syn_$t.vhdl + analyze syn_$t.vhdl tb_$t.vhdl + elab_simulate tb_$t + clean +done + +echo "Test successful" diff --git a/testsuite/synth/synth8/tb_test5.vhdl b/testsuite/synth/synth8/tb_test5.vhdl new file mode 100644 index 000000000..14ef0660e --- /dev/null +++ b/testsuite/synth/synth8/tb_test5.vhdl @@ -0,0 +1,19 @@ +entity tb_test5 is +end tb_test5; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_test5 is + signal r : std_logic_vector(7 downto 0); +begin + dut: entity work.test5 + port map (r); + + process + begin + wait for 1 ns; + assert r(7) = '1' severity failure; + wait; + end process; +end behav; diff --git a/testsuite/synth/synth8/tb_vector8_test1.vhdl b/testsuite/synth/synth8/tb_vector8_test1.vhdl new file mode 100644 index 000000000..0a37884d5 --- /dev/null +++ b/testsuite/synth/synth8/tb_vector8_test1.vhdl @@ -0,0 +1,19 @@ +entity tb_vector8_test1 is +end tb_vector8_test1; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_vector8_test1 is + signal r : std_logic; +begin + dut: entity work.vector8_test1 + port map (r); + + process + begin + wait for 1 ns; + assert r = '1' severity failure; + wait; + end process; +end behav; diff --git a/testsuite/synth/synth8/test2.vhdl b/testsuite/synth/synth8/test2.vhdl new file mode 100644 index 000000000..dca1601bb --- /dev/null +++ b/testsuite/synth/synth8/test2.vhdl @@ -0,0 +1,15 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity test2 is + port (led: out std_logic_vector (7 downto 0)); +end test2; + +architecture synth of test2 is + +begin + led(7) <= '0'; + led(6) <= '1'; +-- led(5) <= '0'; +-- led(3 downto 0) <= x"9"; +end synth; diff --git a/testsuite/synth/synth8/test3.vhdl b/testsuite/synth/synth8/test3.vhdl new file mode 100644 index 000000000..3e17936ca --- /dev/null +++ b/testsuite/synth/synth8/test3.vhdl @@ -0,0 +1,28 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity test3 is + port (led: out std_logic_vector (7 downto 0); + rst : std_logic; + clk : std_logic); +end test3; + +architecture synth of test3 is + signal int : std_logic_vector(1 downto 0); +begin +-- led(7) <= '0'; +-- led(6) <= '1'; +-- led(5) <= '0'; +-- led(3 downto 0) <= x"9"; + process (clk) is + begin + if rising_edge (clk) then + if rst = '1' then + int(1) <= '0'; + else + int(1) <= not int(1); + end if; + end if; + end process; + led(5) <= int (1); +end synth; diff --git a/testsuite/synth/synth8/test4.vhdl b/testsuite/synth/synth8/test4.vhdl new file mode 100644 index 000000000..4875fa1ec --- /dev/null +++ b/testsuite/synth/synth8/test4.vhdl @@ -0,0 +1,28 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity test4 is + port (led: out std_logic_vector (7 downto 0); + rst : std_logic; + clk : std_logic); +end test4; + +architecture synth of test4 is + signal int : std_logic_vector(1 downto 0); +begin +-- led(7) <= '0'; +-- led(6) <= '1'; +-- led(5) <= '0'; +-- led(3 downto 0) <= x"9"; +-- int(0) <= '0'; + process (clk) is + begin + if rst = '1' then + int(1) <= '0'; + elsif rising_edge (clk) then + int(1) <= not int(1); + end if; + end process; + led(5) <= int (1); +-- led(4) <= int(0); +end synth; diff --git a/testsuite/synth/synth8/test5.vhdl b/testsuite/synth/synth8/test5.vhdl new file mode 100644 index 000000000..0d1fbc0e5 --- /dev/null +++ b/testsuite/synth/synth8/test5.vhdl @@ -0,0 +1,15 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity test5 is + port (led: out std_logic_vector (7 downto 0)); +end test5; + +architecture synth of test5 is + +begin + led(7) <= '1'; +-- led(6) <= '1'; +-- led(5) <= '0'; +-- led(3 downto 0) <= x"9"; +end synth; diff --git a/testsuite/synth/synth8/testsuite.sh b/testsuite/synth/synth8/testsuite.sh new file mode 100755 index 000000000..df039cb08 --- /dev/null +++ b/testsuite/synth/synth8/testsuite.sh @@ -0,0 +1,16 @@ +#! /bin/sh + +. ../../testenv.sh + +for t in vector8_test1 test5; do + analyze $t.vhdl tb_$t.vhdl + elab_simulate tb_$t + clean + + synth $t.vhdl -e $t > syn_$t.vhdl + analyze syn_$t.vhdl tb_$t.vhdl + elab_simulate tb_$t + clean +done + +echo "Test successful" diff --git a/testsuite/synth/synth8/vector8_test1.vhdl b/testsuite/synth/synth8/vector8_test1.vhdl new file mode 100644 index 000000000..585d003b0 --- /dev/null +++ b/testsuite/synth/synth8/vector8_test1.vhdl @@ -0,0 +1,16 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity vector8_test1 is + port (led7: out std_logic); +end vector8_test1; + +architecture synth of vector8_test1 is + +signal v : std_logic_vector(7 downto 0); + +begin + v(7) <= '1'; + led7 <= v(7); +end synth; -- cgit v1.2.3