From 6d8dbed5efcbbabbc886beb9a0291e43013010bc Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Thu, 4 Aug 2022 08:56:44 +0200
Subject: testsuite/synth: add a test for #2159

---
 testsuite/synth/issue2159/bug.vhdl     | 21 +++++++++++++++++++++
 testsuite/synth/issue2159/testsuite.sh |  8 ++++++++
 2 files changed, 29 insertions(+)
 create mode 100644 testsuite/synth/issue2159/bug.vhdl
 create mode 100755 testsuite/synth/issue2159/testsuite.sh

(limited to 'testsuite')

diff --git a/testsuite/synth/issue2159/bug.vhdl b/testsuite/synth/issue2159/bug.vhdl
new file mode 100644
index 000000000..0dfd4a2fb
--- /dev/null
+++ b/testsuite/synth/issue2159/bug.vhdl
@@ -0,0 +1,21 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity bug is
+	generic (
+		LEN_DATA     : positive := 32;
+		MAX_STEP     : positive := 8
+	);
+	port (
+		src :  in std_ulogic_vector(LEN_DATA-1 downto 0);
+		dst : out std_ulogic_vector(LEN_DATA-1 downto 0);
+		
+		step : in integer range 0 to MAX_STEP-1
+	);
+end bug;
+
+architecture rtl of bug is
+	constant STEP_SIZE : positive := 2;
+begin
+	dst <= src ror step*STEP_SIZE;
+end architecture;
diff --git a/testsuite/synth/issue2159/testsuite.sh b/testsuite/synth/issue2159/testsuite.sh
new file mode 100755
index 000000000..567d44382
--- /dev/null
+++ b/testsuite/synth/issue2159/testsuite.sh
@@ -0,0 +1,8 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+synth_only bug
+
+echo "Test successful"
-- 
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