From 4cee5eeae85beb7432c8e085da0a5bf8aa1db8a1 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Wed, 22 Sep 2021 19:41:34 +0200 Subject: testsuite/gna: add a test for #1875 --- testsuite/gna/issue1875/test.vhdl | 19 +++++++++++++++++++ testsuite/gna/issue1875/testsuite.sh | 11 +++++++++++ 2 files changed, 30 insertions(+) create mode 100644 testsuite/gna/issue1875/test.vhdl create mode 100755 testsuite/gna/issue1875/testsuite.sh (limited to 'testsuite') diff --git a/testsuite/gna/issue1875/test.vhdl b/testsuite/gna/issue1875/test.vhdl new file mode 100644 index 000000000..e1540e551 --- /dev/null +++ b/testsuite/gna/issue1875/test.vhdl @@ -0,0 +1,19 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.VITAL_timing.all; +use IEEE.VITAL_primitives.all; + +entity test is + port ( + CLK : in std_logic_vector(1 downto 0) + ); + attribute VITAL_LEVEL0 of test : entity is TRUE; +end test; + +architecture VITAL_ACT of test is +begin + process + begin + wait; + end process; +end architecture; diff --git a/testsuite/gna/issue1875/testsuite.sh b/testsuite/gna/issue1875/testsuite.sh new file mode 100755 index 000000000..a3abac41b --- /dev/null +++ b/testsuite/gna/issue1875/testsuite.sh @@ -0,0 +1,11 @@ +#! /bin/sh + +. ../../testenv.sh + +export GHDL_STD_FLAGS="--std=08 -frelaxed" +analyze test.vhdl +elab_simulate test + +clean + +echo "Test successful" -- cgit v1.2.3