From 46b02a2f1217646ee475e5169a372690d88255ea Mon Sep 17 00:00:00 2001 From: Thomas Hiscock Date: Thu, 5 Jan 2017 21:02:13 +0100 Subject: removing PSL coverage hit default report It closes #228. Nothing is displayed unless the user specifies a report statement. Testcase added to check this behaviour. --- testsuite/gna/issue228/tb.vhdl | 61 +++++++++++++++++++++++++++++++++++++ testsuite/gna/issue228/testsuite.sh | 15 +++++++++ 2 files changed, 76 insertions(+) create mode 100644 testsuite/gna/issue228/tb.vhdl create mode 100755 testsuite/gna/issue228/testsuite.sh (limited to 'testsuite') diff --git a/testsuite/gna/issue228/tb.vhdl b/testsuite/gna/issue228/tb.vhdl new file mode 100644 index 000000000..4dfaf3cf3 --- /dev/null +++ b/testsuite/gna/issue228/tb.vhdl @@ -0,0 +1,61 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity foo is + port ( + clk : in std_ulogic; + a0 : in std_ulogic + ); +end entity; + +architecture bar of foo is +begin + -- psl default clock is rising_edge(clk); + -- psl sequence rising_a0 is {not(a0); a0}; + -- psl sequence falling_a0 is {a0; not(a0)}; + -- psl cover {rising_a0}; + -- psl cover {falling_a0} report "falling_a0 custom report"; +end architecture; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity foo_tb is +end entity; + +architecture tb of foo_tb is + signal clk : std_ulogic := '0'; + signal a0 : std_ulogic; +begin + + clk_gen: + process + begin + for i in 0 to 10 loop + clk <= not(clk); + wait for 10 ns; + end loop; + wait; + end process; + + test_driver: + process + begin + a0 <= '1'; + wait until rising_edge(clk); + a0 <= '0'; + wait until rising_edge(clk); + a0 <= '1'; + wait until rising_edge(clk); + wait until rising_edge(clk); + wait; + end process; + + dut: + entity work.foo(bar) + port map ( + clk => clk, + a0 => a0); + +end architecture; diff --git a/testsuite/gna/issue228/testsuite.sh b/testsuite/gna/issue228/testsuite.sh new file mode 100755 index 000000000..437efa718 --- /dev/null +++ b/testsuite/gna/issue228/testsuite.sh @@ -0,0 +1,15 @@ +#! /bin/sh + +. ../../testenv.sh + +GHDL_STD_FLAGS=-fpsl +analyze tb.vhdl +elab_simulate foo_tb 2>sim_log.txt + +run "grep -q 'falling_a0 custom report' sim_log.txt" +run_failure "grep -q 'sequence covered' sim_log.txt" + +rm -f sim_log.txt +clean + +echo "Test successful" -- cgit v1.2.3