From 42949205cecf12b76a93db66e66959584c6033b7 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sun, 13 Dec 2020 20:43:05 +0100
Subject: testsuite/synth: add a test for #1536

---
 testsuite/synth/issue1536/ent1.vhdl    | 14 ++++++++++++++
 testsuite/synth/issue1536/ent2.vhdl    | 14 ++++++++++++++
 testsuite/synth/issue1536/testsuite.sh | 11 +++++++++++
 3 files changed, 39 insertions(+)
 create mode 100644 testsuite/synth/issue1536/ent1.vhdl
 create mode 100644 testsuite/synth/issue1536/ent2.vhdl
 create mode 100755 testsuite/synth/issue1536/testsuite.sh

(limited to 'testsuite')

diff --git a/testsuite/synth/issue1536/ent1.vhdl b/testsuite/synth/issue1536/ent1.vhdl
new file mode 100644
index 000000000..e3f811006
--- /dev/null
+++ b/testsuite/synth/issue1536/ent1.vhdl
@@ -0,0 +1,14 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ent1 is
+    port (
+        i: in bit;
+        o: out std_ulogic
+    );
+end entity;
+
+architecture arch of ent1 is
+begin
+    o <= to_stdulogic(i);
+end architecture;
diff --git a/testsuite/synth/issue1536/ent2.vhdl b/testsuite/synth/issue1536/ent2.vhdl
new file mode 100644
index 000000000..fabf756e8
--- /dev/null
+++ b/testsuite/synth/issue1536/ent2.vhdl
@@ -0,0 +1,14 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ent2 is
+    port (
+        i: in bit_vector(3 downto 0);
+        o: out std_ulogic_vector(3 downto 0)
+    );
+end entity;
+
+architecture arch of ent2 is
+begin
+    o <= to_stdulogicvector(i);
+end architecture;
diff --git a/testsuite/synth/issue1536/testsuite.sh b/testsuite/synth/issue1536/testsuite.sh
new file mode 100755
index 000000000..a7846d914
--- /dev/null
+++ b/testsuite/synth/issue1536/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for f in ent1 ent2 ; do
+  synth_analyze $f
+done
+
+clean
+
+echo "Test successful"
-- 
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