From 3bd9a185da8178e878e8034e04aab2238bab50ff Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sat, 30 Nov 2019 07:43:47 +0100
Subject: testsuite: add case for #1047

---
 testsuite/synth/issue1047/testsuite.sh | 12 ++++++++++
 testsuite/synth/issue1047/top.vhdl     | 41 ++++++++++++++++++++++++++++++++++
 2 files changed, 53 insertions(+)
 create mode 100755 testsuite/synth/issue1047/testsuite.sh
 create mode 100644 testsuite/synth/issue1047/top.vhdl

(limited to 'testsuite')

diff --git a/testsuite/synth/issue1047/testsuite.sh b/testsuite/synth/issue1047/testsuite.sh
new file mode 100755
index 000000000..4ff5449d8
--- /dev/null
+++ b/testsuite/synth/issue1047/testsuite.sh
@@ -0,0 +1,12 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in top; do
+  synth $t.vhdl -e $t > syn_$t.vhdl
+#  analyze syn_$t.vhdl
+done
+
+clean
+
+echo "Test successful"
diff --git a/testsuite/synth/issue1047/top.vhdl b/testsuite/synth/issue1047/top.vhdl
new file mode 100644
index 000000000..dcdb44524
--- /dev/null
+++ b/testsuite/synth/issue1047/top.vhdl
@@ -0,0 +1,41 @@
+library ieee;
+use ieee.std_logic_1164.ALL;
+
+entity child is
+  port (
+    A:  out std_logic
+  );
+end entity child;
+
+architecture rtl of child is
+begin
+  A <= '0';
+end architecture rtl;
+
+
+library ieee;
+use ieee.std_logic_1164.ALL;
+
+entity top is
+  port (
+    A:  out std_logic_vector(1 downto 0)
+  );
+end entity top;
+
+architecture rtl of top is
+  component child is
+    port (
+      A:  out std_logic
+    );
+  end component child;
+
+  constant N:   integer := 2;
+begin
+  CHILDGEN: for i in 0 to N-1 generate
+  begin
+    CHILDINST : child
+      port map(
+        A => A(i)
+      );
+  end generate CHILDGEN;
+end architecture rtl;
-- 
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