From 393612fc52586d8eb8372f0ce3f05c162cfccfe2 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Tue, 18 Feb 2020 18:44:42 +0100 Subject: testsuite/synth: merge ram01 to mem01, add NOTES.txt --- testsuite/synth/mem01/NOTES.txt | 9 ++++++++ testsuite/synth/mem01/sram01.vhdl | 29 ++++++++++++++++++++++++ testsuite/synth/mem01/srom01.vhdl | 28 +++++++++++++++++++++++ testsuite/synth/mem01/tb_sram01.vhdl | 43 ++++++++++++++++++++++++++++++++++++ testsuite/synth/mem01/tb_srom01.vhdl | 38 +++++++++++++++++++++++++++++++ testsuite/synth/mem01/testsuite.sh | 2 +- testsuite/synth/mem02/NOTES.txt | 8 +++++++ testsuite/synth/mem2d01/NOTES.txt | 7 ++++++ testsuite/synth/ram01/sram01.vhdl | 29 ------------------------ testsuite/synth/ram01/srom01.vhdl | 28 ----------------------- testsuite/synth/ram01/tb_sram01.vhdl | 43 ------------------------------------ testsuite/synth/ram01/tb_srom01.vhdl | 38 ------------------------------- testsuite/synth/ram01/testsuite.sh | 16 -------------- 13 files changed, 163 insertions(+), 155 deletions(-) create mode 100644 testsuite/synth/mem01/NOTES.txt create mode 100644 testsuite/synth/mem01/sram01.vhdl create mode 100644 testsuite/synth/mem01/srom01.vhdl create mode 100644 testsuite/synth/mem01/tb_sram01.vhdl create mode 100644 testsuite/synth/mem01/tb_srom01.vhdl create mode 100644 testsuite/synth/mem02/NOTES.txt create mode 100644 testsuite/synth/mem2d01/NOTES.txt delete mode 100644 testsuite/synth/ram01/sram01.vhdl delete mode 100644 testsuite/synth/ram01/srom01.vhdl delete mode 100644 testsuite/synth/ram01/tb_sram01.vhdl delete mode 100644 testsuite/synth/ram01/tb_srom01.vhdl delete mode 100755 testsuite/synth/ram01/testsuite.sh (limited to 'testsuite') diff --git a/testsuite/synth/mem01/NOTES.txt b/testsuite/synth/mem01/NOTES.txt new file mode 100644 index 000000000..84edd5041 --- /dev/null +++ b/testsuite/synth/mem01/NOTES.txt @@ -0,0 +1,9 @@ +Tests for RAMs +-------------- + +rom1: asynchronous ROM +srom01: Read (initialized ROM). +sram01: Read+Write (at the same address). +dpram1: Read+Write (using signals, without enables) +dpram2: Read+Write (using a variable, without enables) +dpram3: Read+Write (like dpram2 but downto) diff --git a/testsuite/synth/mem01/sram01.vhdl b/testsuite/synth/mem01/sram01.vhdl new file mode 100644 index 000000000..b4bfd0d2e --- /dev/null +++ b/testsuite/synth/mem01/sram01.vhdl @@ -0,0 +1,29 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity sram01 is + port ( + clk_i : std_logic; + addr_i : std_logic_vector(3 downto 0); + data_i : std_logic_vector(7 downto 0); + data_o : out std_logic_vector(7 downto 0); + wen_i : std_logic); +end sram01; + +architecture behav of sram01 is +begin + process (clk_i, addr_i) + type mem_type is array (0 to 15) of std_logic_vector (7 downto 0); + variable mem : mem_type; + variable addr : natural range mem_type'range; + begin + if rising_edge(clk_i) then + addr := to_integer (unsigned (addr_i)); + data_o <= mem (addr); + if wen_i = '1' then + mem (addr) := data_i; + end if; + end if; + end process; +end behav; diff --git a/testsuite/synth/mem01/srom01.vhdl b/testsuite/synth/mem01/srom01.vhdl new file mode 100644 index 000000000..1d8e70b64 --- /dev/null +++ b/testsuite/synth/mem01/srom01.vhdl @@ -0,0 +1,28 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity srom01 is + port ( + clk_i : std_logic; + addr_i : std_logic_vector(3 downto 0); + data_o : out std_logic_vector(7 downto 0)); +end srom01; + +architecture behav of srom01 is +begin + process (clk_i, addr_i) + type mem_type is array (0 to 15) of std_logic_vector (7 downto 0); + constant mem : mem_type := ( + x"f0", x"e1", x"d2", x"c3", + x"b4", x"a5", x"96", x"87", + x"78", x"69", x"5a", x"4b", + x"3c", x"2d", x"1e", x"0f"); + variable addr : natural range mem_type'range; + begin + if rising_edge(clk_i) then + addr := to_integer (unsigned (addr_i)); + data_o <= mem (addr); + end if; + end process; +end behav; diff --git a/testsuite/synth/mem01/tb_sram01.vhdl b/testsuite/synth/mem01/tb_sram01.vhdl new file mode 100644 index 000000000..6fa0a7106 --- /dev/null +++ b/testsuite/synth/mem01/tb_sram01.vhdl @@ -0,0 +1,43 @@ +entity tb_sram01 is +end tb_sram01; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_sram01 is + signal addr : std_logic_vector(3 downto 0); + signal rdat : std_logic_vector(7 downto 0); + signal wdat : std_logic_vector(7 downto 0); + signal wen : std_logic; + signal clk : std_logic; +begin + dut: entity work.sram01 + port map (clk_i => clk, addr_i => addr, data_i => wdat, data_o => rdat, + wen_i => wen); + + process + procedure pulse is + begin + clk <= '0'; + wait for 1 ns; + clk <= '1'; + wait for 1 ns; + end pulse; + begin + addr <= "0000"; + wdat <= x"01"; + wen <= '1'; + pulse; + + addr <= "0001"; + wdat <= x"02"; + pulse; + + addr <= "0000"; + wen <= '0'; + pulse; + assert rdat = x"01" severity failure; + + wait; + end process; +end behav; diff --git a/testsuite/synth/mem01/tb_srom01.vhdl b/testsuite/synth/mem01/tb_srom01.vhdl new file mode 100644 index 000000000..530423a67 --- /dev/null +++ b/testsuite/synth/mem01/tb_srom01.vhdl @@ -0,0 +1,38 @@ +entity tb_srom01 is +end tb_srom01; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_srom01 is + signal addr : std_logic_vector(3 downto 0); + signal rdat : std_logic_vector(7 downto 0); + signal clk : std_logic; +begin + dut: entity work.srom01 + port map (clk_i => clk, addr_i => addr, data_o => rdat); + + process + procedure pulse is + begin + clk <= '0'; + wait for 1 ns; + clk <= '1'; + wait for 1 ns; + end pulse; + begin + addr <= "0000"; + pulse; + assert rdat = x"f0" severity failure; + + addr <= "0001"; + pulse; + assert rdat = x"e1" severity failure; + + addr <= "0100"; + pulse; + assert rdat = x"b4" severity failure; + + wait; + end process; +end behav; diff --git a/testsuite/synth/mem01/testsuite.sh b/testsuite/synth/mem01/testsuite.sh index 8d0b840a5..073c69ea4 100755 --- a/testsuite/synth/mem01/testsuite.sh +++ b/testsuite/synth/mem01/testsuite.sh @@ -2,7 +2,7 @@ . ../../testenv.sh -for t in rom1 dpram1 dpram2 dpram3; do +for t in rom1 srom01 sram01 dpram1 dpram2 dpram3; do analyze $t.vhdl tb_$t.vhdl elab_simulate tb_$t clean diff --git a/testsuite/synth/mem02/NOTES.txt b/testsuite/synth/mem02/NOTES.txt new file mode 100644 index 000000000..fa43cedc9 --- /dev/null +++ b/testsuite/synth/mem02/NOTES.txt @@ -0,0 +1,8 @@ +Tests for RAMs +-------------- + +dpram1: Read+Write (using a signal) +ram3: not a RAM (whole content available on a port). +ram4: not a RAM (reset). +ram5: not a RAM (reset) +ram6: not a RAM (whole content available). diff --git a/testsuite/synth/mem2d01/NOTES.txt b/testsuite/synth/mem2d01/NOTES.txt new file mode 100644 index 000000000..17ed281fb --- /dev/null +++ b/testsuite/synth/mem2d01/NOTES.txt @@ -0,0 +1,7 @@ +Tests for RAMs +-------------- + +dpram1r: Read(2d)+Write(1d), using indexes +dpram2r: Read(2d)+Write(1d), using slices. +dpram2w: Read(1d)+Write(2d), using slices. +memmux04: Read(2d)+Write(1d), enable on write, intermediate variable for read. diff --git a/testsuite/synth/ram01/sram01.vhdl b/testsuite/synth/ram01/sram01.vhdl deleted file mode 100644 index b4bfd0d2e..000000000 --- a/testsuite/synth/ram01/sram01.vhdl +++ /dev/null @@ -1,29 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity sram01 is - port ( - clk_i : std_logic; - addr_i : std_logic_vector(3 downto 0); - data_i : std_logic_vector(7 downto 0); - data_o : out std_logic_vector(7 downto 0); - wen_i : std_logic); -end sram01; - -architecture behav of sram01 is -begin - process (clk_i, addr_i) - type mem_type is array (0 to 15) of std_logic_vector (7 downto 0); - variable mem : mem_type; - variable addr : natural range mem_type'range; - begin - if rising_edge(clk_i) then - addr := to_integer (unsigned (addr_i)); - data_o <= mem (addr); - if wen_i = '1' then - mem (addr) := data_i; - end if; - end if; - end process; -end behav; diff --git a/testsuite/synth/ram01/srom01.vhdl b/testsuite/synth/ram01/srom01.vhdl deleted file mode 100644 index 1d8e70b64..000000000 --- a/testsuite/synth/ram01/srom01.vhdl +++ /dev/null @@ -1,28 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity srom01 is - port ( - clk_i : std_logic; - addr_i : std_logic_vector(3 downto 0); - data_o : out std_logic_vector(7 downto 0)); -end srom01; - -architecture behav of srom01 is -begin - process (clk_i, addr_i) - type mem_type is array (0 to 15) of std_logic_vector (7 downto 0); - constant mem : mem_type := ( - x"f0", x"e1", x"d2", x"c3", - x"b4", x"a5", x"96", x"87", - x"78", x"69", x"5a", x"4b", - x"3c", x"2d", x"1e", x"0f"); - variable addr : natural range mem_type'range; - begin - if rising_edge(clk_i) then - addr := to_integer (unsigned (addr_i)); - data_o <= mem (addr); - end if; - end process; -end behav; diff --git a/testsuite/synth/ram01/tb_sram01.vhdl b/testsuite/synth/ram01/tb_sram01.vhdl deleted file mode 100644 index 6fa0a7106..000000000 --- a/testsuite/synth/ram01/tb_sram01.vhdl +++ /dev/null @@ -1,43 +0,0 @@ -entity tb_sram01 is -end tb_sram01; - -library ieee; -use ieee.std_logic_1164.all; - -architecture behav of tb_sram01 is - signal addr : std_logic_vector(3 downto 0); - signal rdat : std_logic_vector(7 downto 0); - signal wdat : std_logic_vector(7 downto 0); - signal wen : std_logic; - signal clk : std_logic; -begin - dut: entity work.sram01 - port map (clk_i => clk, addr_i => addr, data_i => wdat, data_o => rdat, - wen_i => wen); - - process - procedure pulse is - begin - clk <= '0'; - wait for 1 ns; - clk <= '1'; - wait for 1 ns; - end pulse; - begin - addr <= "0000"; - wdat <= x"01"; - wen <= '1'; - pulse; - - addr <= "0001"; - wdat <= x"02"; - pulse; - - addr <= "0000"; - wen <= '0'; - pulse; - assert rdat = x"01" severity failure; - - wait; - end process; -end behav; diff --git a/testsuite/synth/ram01/tb_srom01.vhdl b/testsuite/synth/ram01/tb_srom01.vhdl deleted file mode 100644 index 530423a67..000000000 --- a/testsuite/synth/ram01/tb_srom01.vhdl +++ /dev/null @@ -1,38 +0,0 @@ -entity tb_srom01 is -end tb_srom01; - -library ieee; -use ieee.std_logic_1164.all; - -architecture behav of tb_srom01 is - signal addr : std_logic_vector(3 downto 0); - signal rdat : std_logic_vector(7 downto 0); - signal clk : std_logic; -begin - dut: entity work.srom01 - port map (clk_i => clk, addr_i => addr, data_o => rdat); - - process - procedure pulse is - begin - clk <= '0'; - wait for 1 ns; - clk <= '1'; - wait for 1 ns; - end pulse; - begin - addr <= "0000"; - pulse; - assert rdat = x"f0" severity failure; - - addr <= "0001"; - pulse; - assert rdat = x"e1" severity failure; - - addr <= "0100"; - pulse; - assert rdat = x"b4" severity failure; - - wait; - end process; -end behav; diff --git a/testsuite/synth/ram01/testsuite.sh b/testsuite/synth/ram01/testsuite.sh deleted file mode 100755 index 6254b1ab6..000000000 --- a/testsuite/synth/ram01/testsuite.sh +++ /dev/null @@ -1,16 +0,0 @@ -#! /bin/sh - -. ../../testenv.sh - -for t in sram01 srom01; do - analyze $t.vhdl tb_$t.vhdl - elab_simulate tb_$t - clean - - synth $t.vhdl -e $t > syn_$t.vhdl - analyze syn_$t.vhdl tb_$t.vhdl - elab_simulate tb_$t --ieee-asserts=disable-at-0 - clean -done - -echo "Test successful" -- cgit v1.2.3