From 3145f5665bf2aef67d9da88538e16d3790f3c377 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Mon, 11 Apr 2022 18:23:03 +0200 Subject: testsuite/gna: add a test for #2031 --- testsuite/gna/issue2031/entity.vhdl | 15 +++++++++++++++ testsuite/gna/issue2031/testbench.vhdl | 20 ++++++++++++++++++++ testsuite/gna/issue2031/testsuite.sh | 11 +++++++++++ 3 files changed, 46 insertions(+) create mode 100644 testsuite/gna/issue2031/entity.vhdl create mode 100644 testsuite/gna/issue2031/testbench.vhdl create mode 100755 testsuite/gna/issue2031/testsuite.sh (limited to 'testsuite') diff --git a/testsuite/gna/issue2031/entity.vhdl b/testsuite/gna/issue2031/entity.vhdl new file mode 100644 index 000000000..3af6aef9d --- /dev/null +++ b/testsuite/gna/issue2031/entity.vhdl @@ -0,0 +1,15 @@ +library IEEE; +use IEEE.std_logic_1164.all; + +entity abc is + port( + a : std_logic; + b : std_logic; + c : out std_logic + ); +end entity; + +architecture arch of abc is +begin + c <= a and b; +end architecture; diff --git a/testsuite/gna/issue2031/testbench.vhdl b/testsuite/gna/issue2031/testbench.vhdl new file mode 100644 index 000000000..3807e4485 --- /dev/null +++ b/testsuite/gna/issue2031/testbench.vhdl @@ -0,0 +1,20 @@ +library Bugtests; +use Bugtests.abc.all; + +library IEEE; +use IEEE.std_logic_1164.all; + +entity test is + +end entity; + +architecture arch_test of test is + signal tb : std_logic; +begin + DUT: entity Bugtests.abc + port map( + a => '1', + b => '0', + c => tb + ); +end architecture; diff --git a/testsuite/gna/issue2031/testsuite.sh b/testsuite/gna/issue2031/testsuite.sh new file mode 100755 index 000000000..2aa5ab035 --- /dev/null +++ b/testsuite/gna/issue2031/testsuite.sh @@ -0,0 +1,11 @@ +#! /bin/sh + +. ../../testenv.sh + +analyze --work=bugtests entity.vhdl +analyze_failure --work=bugtests testbench.vhdl 2> testbench.err +grep "prefix must designate" testbench.err | grep "testbench.vhdl" + +clean bugtests + +echo "Test successful" -- cgit v1.2.3