From 2e6cf50ff058c46b545385be33f331430f75f5d9 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Wed, 21 Dec 2022 20:56:42 +0100
Subject: testsuite/gna: add a test for #2277

---
 testsuite/gna/issue2277/ent.vhdl     | 38 ++++++++++++++++++++++++++++++++++++
 testsuite/gna/issue2277/testsuite.sh | 12 ++++++++++++
 2 files changed, 50 insertions(+)
 create mode 100644 testsuite/gna/issue2277/ent.vhdl
 create mode 100755 testsuite/gna/issue2277/testsuite.sh

(limited to 'testsuite')

diff --git a/testsuite/gna/issue2277/ent.vhdl b/testsuite/gna/issue2277/ent.vhdl
new file mode 100644
index 000000000..0b03be8d6
--- /dev/null
+++ b/testsuite/gna/issue2277/ent.vhdl
@@ -0,0 +1,38 @@
+library ieee;
+use ieee.std_logic_1164.all;
+entity test_entity_assert is
+  port (
+    i_clk : in  std_ulogic;
+    o_clk : out std_ulogic
+    );
+end entity;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity simple_configuration_specification_2 is
+end entity;
+
+architecture arch of simple_configuration_specification_2 is
+  signal s_clk : std_ulogic;
+
+  component test_entity_assert is
+    port (
+      i_clk : in  std_ulogic;
+      o_clk : out std_ulogic
+      );
+  end component;
+
+  -- the following should be parsed
+  for inst_test_entity_assert : test_entity_assert
+    use entity work.test_entity_assert;
+  end for;
+begin
+
+  inst_test_entity_assert : test_entity_assert
+    port map (
+      i_clk => s_clk,
+      o_clk => s_clk
+      );
+
+end architecture;
diff --git a/testsuite/gna/issue2277/testsuite.sh b/testsuite/gna/issue2277/testsuite.sh
new file mode 100755
index 000000000..c1c906697
--- /dev/null
+++ b/testsuite/gna/issue2277/testsuite.sh
@@ -0,0 +1,12 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+analyze_failure ent.vhdl
+
+export GHDL_STD_FLAGS=--std=08
+analyze ent.vhdl
+
+clean
+
+echo "Test successful"
-- 
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