From 2e12aa8732cd49438a165a0b20c9acd9e37cde4d Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Tue, 1 Oct 2019 20:29:13 +0200 Subject: testsuite/synth: add testcases for #958 --- testsuite/synth/issue958/ent.vhdl | 19 +++++++++++++++++++ testsuite/synth/issue958/ent1.vhdl | 21 +++++++++++++++++++++ testsuite/synth/issue958/testsuite.sh | 11 +++++++++++ 3 files changed, 51 insertions(+) create mode 100644 testsuite/synth/issue958/ent.vhdl create mode 100644 testsuite/synth/issue958/ent1.vhdl create mode 100755 testsuite/synth/issue958/testsuite.sh (limited to 'testsuite') diff --git a/testsuite/synth/issue958/ent.vhdl b/testsuite/synth/issue958/ent.vhdl new file mode 100644 index 000000000..8926ae673 --- /dev/null +++ b/testsuite/synth/issue958/ent.vhdl @@ -0,0 +1,19 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity ent is +end; + +architecture a of ent is + component c is + port ( + p : in std_logic_vector(7 downto 0) + ); + end component; +begin + inst: component c + port map ( + p => x"00" + ); +end; + diff --git a/testsuite/synth/issue958/ent1.vhdl b/testsuite/synth/issue958/ent1.vhdl new file mode 100644 index 000000000..daf5e1e0c --- /dev/null +++ b/testsuite/synth/issue958/ent1.vhdl @@ -0,0 +1,21 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity ent1 is +end; + +architecture a of ent1 is + component c is + port ( + p : in std_logic_vector(7 downto 0) + ); + end component; + signal s : std_logic_vector(7 downto 0); +begin + inst: component c + port map ( + p => s + ); + s <= x"01"; +end; + diff --git a/testsuite/synth/issue958/testsuite.sh b/testsuite/synth/issue958/testsuite.sh new file mode 100755 index 000000000..02e38f330 --- /dev/null +++ b/testsuite/synth/issue958/testsuite.sh @@ -0,0 +1,11 @@ +#! /bin/sh + +. ../../testenv.sh + +for f in ent ent1; do + synth $f.vhdl -e $f > syn_$f.vhdl + analyze syn_$f.vhdl + clean +done + +echo "Test successful" -- cgit v1.2.3