From 2ae368913e5e000ab40f48468cbc6981217861cc Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Tue, 4 Oct 2022 13:11:33 +0200
Subject: testsuite/synth: add a reproducer for #2205

---
 testsuite/synth/issue2205/repro.vhdl   | 33 +++++++++++++++++++++++++++++++++
 testsuite/synth/issue2205/testsuite.sh |  7 +++++++
 2 files changed, 40 insertions(+)
 create mode 100644 testsuite/synth/issue2205/repro.vhdl
 create mode 100755 testsuite/synth/issue2205/testsuite.sh

(limited to 'testsuite')

diff --git a/testsuite/synth/issue2205/repro.vhdl b/testsuite/synth/issue2205/repro.vhdl
new file mode 100644
index 000000000..f28bb89d1
--- /dev/null
+++ b/testsuite/synth/issue2205/repro.vhdl
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity repro is
+  port (
+    clk_i  : std_logic;
+    addr_i : std_logic_vector(3 downto 0);
+    data_i : std_logic_vector(7 downto 0);
+    data_o : out std_logic_vector(7 downto 0);
+    wen_i   : std_logic);
+end repro;
+
+architecture behav of repro is
+begin
+  process (clk_i, addr_i)
+    variable mem : std_logic_vector(0 to 8*16 - 1);
+    variable addr : natural range 0 to 15;
+
+    impure function rd(ad : natural) return std_logic_vector is
+    begin
+      return mem(ad*8 to ad*8 + 7);
+    end rd;
+  begin
+    if rising_edge(clk_i) then
+      addr := to_integer (unsigned (addr_i));
+      data_o <= rd (addr);
+      if wen_i = '1' then
+        mem (addr*8 to addr*8 + 7) := data_i;
+      end if;
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue2205/testsuite.sh b/testsuite/synth/issue2205/testsuite.sh
new file mode 100755
index 000000000..e9dc72228
--- /dev/null
+++ b/testsuite/synth/issue2205/testsuite.sh
@@ -0,0 +1,7 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth_only repro
+
+echo "Test successful"
-- 
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