From 2129c8a80b66baaabce48bcee92551865de86e74 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Thu, 26 Sep 2019 07:45:48 +0200
Subject: testsuite/synth: add testcase for single bit memory.

---
 testsuite/synth/mem02/ram3.vhdl    | 25 +++++++++++++++++++++++++
 testsuite/synth/mem02/tb_ram3.vhdl | 38 ++++++++++++++++++++++++++++++++++++++
 testsuite/synth/mem02/testsuite.sh |  2 +-
 3 files changed, 64 insertions(+), 1 deletion(-)
 create mode 100644 testsuite/synth/mem02/ram3.vhdl
 create mode 100644 testsuite/synth/mem02/tb_ram3.vhdl

(limited to 'testsuite')

diff --git a/testsuite/synth/mem02/ram3.vhdl b/testsuite/synth/mem02/ram3.vhdl
new file mode 100644
index 000000000..d67667c3e
--- /dev/null
+++ b/testsuite/synth/mem02/ram3.vhdl
@@ -0,0 +1,25 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity ram3 is
+  port (val : out std_logic_vector (7 downto 0);
+        waddr : std_logic_vector (2 downto 0);
+        wdat : std_logic;
+        clk : std_logic);
+end ram3;
+
+architecture behav of ram3 is
+  signal mem : std_logic_vector(7 downto 0);
+begin
+  process (clk)
+    variable ra : natural;
+    variable wa : natural;
+  begin
+    if rising_edge (clk) then
+      ra := to_integer(unsigned (waddr));
+      mem(ra) <= wdat;
+    end if;
+  end process;
+  val <= mem;
+end behav;
diff --git a/testsuite/synth/mem02/tb_ram3.vhdl b/testsuite/synth/mem02/tb_ram3.vhdl
new file mode 100644
index 000000000..d926e9481
--- /dev/null
+++ b/testsuite/synth/mem02/tb_ram3.vhdl
@@ -0,0 +1,38 @@
+entity tb_ram3 is
+end tb_ram3;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_ram3 is
+  signal val : std_logic_vector(7 downto 0);
+  signal waddr : std_logic_vector(2 downto 0);
+  signal wdat : std_logic;
+  signal clk : std_logic;
+begin
+  dut: entity work.ram3
+    port map (waddr => waddr, wdat => wdat, val => val,
+              clk => clk);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    waddr <= "000";
+    wdat <= '0';
+    pulse;
+    
+    waddr <= "001";
+    wdat <= '1';
+    pulse;
+
+    assert (val and x"03") = x"02" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/mem02/testsuite.sh b/testsuite/synth/mem02/testsuite.sh
index ace30ab35..2d7da25bd 100755
--- a/testsuite/synth/mem02/testsuite.sh
+++ b/testsuite/synth/mem02/testsuite.sh
@@ -2,7 +2,7 @@
 
 . ../../testenv.sh
 
-for t in dpram1; do
+for t in dpram1 ram3; do
     analyze $t.vhdl tb_$t.vhdl
     elab_simulate tb_$t
     clean
-- 
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