From 1666a4c7458a9078daa77058ef6173bf34223018 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Wed, 17 Jun 2020 21:58:11 +0200
Subject: testsuite/gna: add tests for #1257

---
 testsuite/gna/issue1257/direction_mismatch.vhd    | 32 +++++++++++++++++++++++
 testsuite/gna/issue1257/repro1.vhdl               | 12 +++++++++
 testsuite/gna/issue1257/repro2.vhdl               | 14 ++++++++++
 testsuite/gna/issue1257/repro3.vhdl               | 15 +++++++++++
 testsuite/gna/issue1257/tb_direction_mismatch.vhd | 15 +++++++++++
 testsuite/gna/issue1257/testsuite.sh              | 20 ++++++++++++++
 6 files changed, 108 insertions(+)
 create mode 100644 testsuite/gna/issue1257/direction_mismatch.vhd
 create mode 100644 testsuite/gna/issue1257/repro1.vhdl
 create mode 100644 testsuite/gna/issue1257/repro2.vhdl
 create mode 100644 testsuite/gna/issue1257/repro3.vhdl
 create mode 100644 testsuite/gna/issue1257/tb_direction_mismatch.vhd
 create mode 100755 testsuite/gna/issue1257/testsuite.sh

(limited to 'testsuite')

diff --git a/testsuite/gna/issue1257/direction_mismatch.vhd b/testsuite/gna/issue1257/direction_mismatch.vhd
new file mode 100644
index 000000000..b420411fc
--- /dev/null
+++ b/testsuite/gna/issue1257/direction_mismatch.vhd
@@ -0,0 +1,32 @@
+library ieee;
+context ieee.ieee_std_context;
+use ieee.math_real.all;
+
+entity direction_mismatch is
+    port (
+        left : out std_logic_vector(1 to 0)
+    );
+end entity direction_mismatch;
+
+architecture rtl of direction_mismatch is
+    constant c : std_logic_vector(1 downto 0) := "01";
+    -- function that can flip words around the center axis of an SLV
+    -- ex. input=0x002_001, width=12, output=0x001_002
+    -- ex. input=0x03_02_01, width=8, output=0x01_02_03
+    function wordrevorder (
+        arg   : std_logic_vector;
+        width : positive
+    )
+    return std_logic_vector is
+        constant c_ratio : integer := arg'length/width;
+        variable v_ret : std_logic_vector(arg'range);
+    begin
+        for i in 0 to c_ratio-1 loop
+            v_ret((i*width)+width-1 downto (i*width)) :=
+                arg(((c_ratio-i-1)*width)+width-1 downto ((c_ratio-i-1)*width));
+        end loop;
+        return v_ret;
+    end;
+begin
+    left <= wordrevorder(c, 1);
+end architecture;
\ No newline at end of file
diff --git a/testsuite/gna/issue1257/repro1.vhdl b/testsuite/gna/issue1257/repro1.vhdl
new file mode 100644
index 000000000..e36835107
--- /dev/null
+++ b/testsuite/gna/issue1257/repro1.vhdl
@@ -0,0 +1,12 @@
+entity repro1 is
+end repro1;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of repro1 is
+   signal left : std_logic_vector(1 downto 0);
+   signal right : std_logic_vector(2 downto 0);
+begin
+    left <= right;
+end;
diff --git a/testsuite/gna/issue1257/repro2.vhdl b/testsuite/gna/issue1257/repro2.vhdl
new file mode 100644
index 000000000..36a4b224b
--- /dev/null
+++ b/testsuite/gna/issue1257/repro2.vhdl
@@ -0,0 +1,14 @@
+entity repro2 is
+end repro2;
+
+architecture behav of repro2 is
+   signal left : bit_vector(1 downto 0);
+begin
+    process
+    begin
+      for i in 1 to 2 loop
+        left(i) <= '1';
+      end loop;
+      wait;
+    end process;
+end;
diff --git a/testsuite/gna/issue1257/repro3.vhdl b/testsuite/gna/issue1257/repro3.vhdl
new file mode 100644
index 000000000..70943b109
--- /dev/null
+++ b/testsuite/gna/issue1257/repro3.vhdl
@@ -0,0 +1,15 @@
+entity repro3 is
+  generic (hi : natural := 1);
+end repro3;
+
+architecture behav of repro3 is
+   signal left : bit_vector(hi downto 0);
+begin
+    process
+    begin
+      for i in 1 to 2 loop
+        left(i) <= '1';
+      end loop;
+      wait;
+    end process;
+end;
diff --git a/testsuite/gna/issue1257/tb_direction_mismatch.vhd b/testsuite/gna/issue1257/tb_direction_mismatch.vhd
new file mode 100644
index 000000000..e7c591c8a
--- /dev/null
+++ b/testsuite/gna/issue1257/tb_direction_mismatch.vhd
@@ -0,0 +1,15 @@
+library ieee;
+context ieee.ieee_std_context;
+
+
+entity tb_direction_mismatch is
+end entity tb_direction_mismatch;
+
+architecture tb of tb_direction_mismatch is
+    signal left : std_logic_vector(1 to 0);
+begin
+    uut : entity work.direction_mismatch
+    port map (
+        left => left
+    );
+end architecture;
diff --git a/testsuite/gna/issue1257/testsuite.sh b/testsuite/gna/issue1257/testsuite.sh
new file mode 100755
index 000000000..d3e8ab9e6
--- /dev/null
+++ b/testsuite/gna/issue1257/testsuite.sh
@@ -0,0 +1,20 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+analyze_failure -Werror=runtime-error repro1.vhdl
+
+analyze repro2.vhdl
+elab_simulate_failure repro2 | tee repro2.err
+grep "1 downto 0" repro2.err
+
+analyze repro3.vhdl
+elab_simulate_failure repro3 | tee repro3.err
+grep "1 downto 0" repro3.err
+
+GHDL_STD_FLAGS=--std=08
+analyze direction_mismatch.vhd  tb_direction_mismatch.vhd
+elab_simulate_failure  tb_direction_mismatch
+clean
+
+echo "Test successful"
-- 
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