From 0f7bdd76d45a453b226ac58ae289bd21cfeb62c2 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Tue, 18 Sep 2018 04:48:39 +0200 Subject: Add testcase for #649 --- testsuite/gna/issue649/ice.vhdl | 11 +++++++++++ testsuite/gna/issue649/repro.vhdl | 12 ++++++++++++ testsuite/gna/issue649/testsuite.sh | 13 +++++++++++++ 3 files changed, 36 insertions(+) create mode 100644 testsuite/gna/issue649/ice.vhdl create mode 100644 testsuite/gna/issue649/repro.vhdl create mode 100755 testsuite/gna/issue649/testsuite.sh (limited to 'testsuite') diff --git a/testsuite/gna/issue649/ice.vhdl b/testsuite/gna/issue649/ice.vhdl new file mode 100644 index 000000000..47b5d3bdd --- /dev/null +++ b/testsuite/gna/issue649/ice.vhdl @@ -0,0 +1,11 @@ +entity e is end entity; +library ieee; +architecture h of e is + constant L :positive := integer(ieee.math_real.ceil(9.9)); + signal s :bit_vector(31 downto 0); + alias a :bit_vector(L-1 downto 2) is s(L-1 downto 2); + signal b :bit_vector(L-1 downto 2); +begin + a <= b; +end architecture; + diff --git a/testsuite/gna/issue649/repro.vhdl b/testsuite/gna/issue649/repro.vhdl new file mode 100644 index 000000000..fe23ad7f7 --- /dev/null +++ b/testsuite/gna/issue649/repro.vhdl @@ -0,0 +1,12 @@ +entity repro is +end entity; + +architecture h of repro is + constant L :positive := 9 + now / 1 ns; + signal s :bit_vector(31 downto 0); + alias a :bit_vector(L-1 downto 2) is s(L-1 downto 2); + signal b :bit_vector(L-1 downto 2); +begin + a <= b; +end architecture; + diff --git a/testsuite/gna/issue649/testsuite.sh b/testsuite/gna/issue649/testsuite.sh new file mode 100755 index 000000000..4f0865456 --- /dev/null +++ b/testsuite/gna/issue649/testsuite.sh @@ -0,0 +1,13 @@ +#! /bin/sh + +. ../../testenv.sh + +analyze ice.vhdl +elab_simulate e + +analyze repro.vhdl +elab_simulate repro + +clean + +echo "Test successful" -- cgit v1.2.3