From f05bbd02f16d3368e9c171a7f42a08f26219262d Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Thu, 22 Dec 2022 08:09:08 +0100
Subject: testsuite/synth: add a test for #2279

---
 testsuite/synth/issue2279/aggr1.vhdl    | 17 +++++++++++++++++
 testsuite/synth/issue2279/ent.vhdl      | 18 ++++++++++++++++++
 testsuite/synth/issue2279/tb_aggr1.vhdl | 29 +++++++++++++++++++++++++++++
 testsuite/synth/issue2279/testsuite.sh  | 11 +++++++++++
 4 files changed, 75 insertions(+)
 create mode 100644 testsuite/synth/issue2279/aggr1.vhdl
 create mode 100644 testsuite/synth/issue2279/ent.vhdl
 create mode 100644 testsuite/synth/issue2279/tb_aggr1.vhdl
 create mode 100755 testsuite/synth/issue2279/testsuite.sh

(limited to 'testsuite/synth')

diff --git a/testsuite/synth/issue2279/aggr1.vhdl b/testsuite/synth/issue2279/aggr1.vhdl
new file mode 100644
index 000000000..13a224d55
--- /dev/null
+++ b/testsuite/synth/issue2279/aggr1.vhdl
@@ -0,0 +1,17 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity aggr1 is
+    generic(
+        DATA_WIDTH : integer := 8
+        );
+    port (a : out std_logic_vector(DATA_WIDTH-1 downto 0);
+          b : out std_logic;
+          c : std_logic_vector(DATA_WIDTH+1-1 downto 0));
+end;
+
+architecture arch of aggr1 is
+begin
+    (a, b) <= c;
+end;
+
diff --git a/testsuite/synth/issue2279/ent.vhdl b/testsuite/synth/issue2279/ent.vhdl
new file mode 100644
index 000000000..6c33c60d3
--- /dev/null
+++ b/testsuite/synth/issue2279/ent.vhdl
@@ -0,0 +1,18 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity ent is
+    generic(
+        DATA_WIDTH : integer := 8
+    );
+end;
+
+architecture arch of ent is
+    signal a : std_logic_vector(DATA_WIDTH-1 downto 0);
+    signal b : std_logic;
+    signal c : std_logic_vector(DATA_WIDTH+1-1 downto 0);
+begin
+    (a, b) <= c;
+end;
+
diff --git a/testsuite/synth/issue2279/tb_aggr1.vhdl b/testsuite/synth/issue2279/tb_aggr1.vhdl
new file mode 100644
index 000000000..60ba4c559
--- /dev/null
+++ b/testsuite/synth/issue2279/tb_aggr1.vhdl
@@ -0,0 +1,29 @@
+entity tb_aggr1 is
+end tb_aggr1;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_aggr1 is
+  signal a : std_logic_vector(7 downto 0);
+  signal b : std_logic;
+  signal c : std_logic_vector(8 downto 0);
+begin
+  dut: entity work.aggr1
+    port map (a, b, c);
+
+  process
+  begin
+    c <= b"1_1100_0011";
+    wait for 1 ns;
+    assert a = x"e1" severity failure;
+    assert b = '1' severity failure;
+
+    c <= b"0_1100_0100";
+    wait for 1 ns;
+    assert a = x"62" severity failure;
+    assert b = '0' severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue2279/testsuite.sh b/testsuite/synth/issue2279/testsuite.sh
new file mode 100755
index 000000000..74c928a61
--- /dev/null
+++ b/testsuite/synth/issue2279/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+
+synth_only ent
+
+synth_tb aggr1
+
+echo "Test successful"
-- 
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