From de8bb483b7adf998644b61119271fb797a1fb032 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Thu, 21 Apr 2022 07:23:40 +0200
Subject: testsuite/synth: add a test for #2041

---
 testsuite/synth/issue2041/mymodule.vhdl | 33 +++++++++++++++++++++++++++++++++
 testsuite/synth/issue2041/testsuite.sh  |  8 ++++++++
 2 files changed, 41 insertions(+)
 create mode 100644 testsuite/synth/issue2041/mymodule.vhdl
 create mode 100755 testsuite/synth/issue2041/testsuite.sh

(limited to 'testsuite/synth')

diff --git a/testsuite/synth/issue2041/mymodule.vhdl b/testsuite/synth/issue2041/mymodule.vhdl
new file mode 100644
index 000000000..124d9f2f6
--- /dev/null
+++ b/testsuite/synth/issue2041/mymodule.vhdl
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity mymodule is
+  port (
+    clk: in std_logic;
+    reset: in std_logic;
+    i: in std_logic_vector(1 downto 0);
+    o: out std_logic
+  );
+end mymodule;
+
+architecture rtl of mymodule is
+signal o_next: std_logic;
+begin
+process(i) begin
+  o_next <= '0';
+  case i is
+    when "00" => o_next <= '0';
+    when others => o_next <= '1';
+  end case;
+end process;
+
+process(clk, reset) begin
+  if rising_edge(clk) then
+    if reset = '1' then
+      o <= '0';
+    else
+      o <= o_next;
+    end if;
+  end if;
+end process;
+end rtl ;
diff --git a/testsuite/synth/issue2041/testsuite.sh b/testsuite/synth/issue2041/testsuite.sh
new file mode 100755
index 000000000..e5c91ff5c
--- /dev/null
+++ b/testsuite/synth/issue2041/testsuite.sh
@@ -0,0 +1,8 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth --out=verilog mymodule.vhdl -e > syn_mymodule.v
+grep -q default syn_mymodule.v
+
+echo "Test successful"
-- 
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