From cb3e7b0f954f91c7a1d4702006b18d0041d6eb0d Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Tue, 9 Aug 2022 21:45:11 +0200
Subject: testsuite/synth: add a test for #2169

---
 testsuite/synth/issue2169/bug.vhdl     | 17 +++++++++++++++++
 testsuite/synth/issue2169/mul.vhdl     | 17 +++++++++++++++++
 testsuite/synth/issue2169/tb.vhdl      | 31 +++++++++++++++++++++++++++++++
 testsuite/synth/issue2169/tb_mul.vhdl  | 31 +++++++++++++++++++++++++++++++
 testsuite/synth/issue2169/testsuite.sh |  7 +++++++
 5 files changed, 103 insertions(+)
 create mode 100644 testsuite/synth/issue2169/bug.vhdl
 create mode 100644 testsuite/synth/issue2169/mul.vhdl
 create mode 100644 testsuite/synth/issue2169/tb.vhdl
 create mode 100644 testsuite/synth/issue2169/tb_mul.vhdl
 create mode 100755 testsuite/synth/issue2169/testsuite.sh

(limited to 'testsuite/synth')

diff --git a/testsuite/synth/issue2169/bug.vhdl b/testsuite/synth/issue2169/bug.vhdl
new file mode 100644
index 000000000..1233d91e1
--- /dev/null
+++ b/testsuite/synth/issue2169/bug.vhdl
@@ -0,0 +1,17 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity bug is
+	port(
+		a :  in unsigned( 7 downto 0);
+		b :  in unsigned(15 downto 0);
+		r : out unsigned(23 downto 0)
+	);
+end entity;
+
+architecture rtl of bug is
+
+begin
+	r <= resize(a*b, 24);
+end architecture;
diff --git a/testsuite/synth/issue2169/mul.vhdl b/testsuite/synth/issue2169/mul.vhdl
new file mode 100644
index 000000000..6a32b7692
--- /dev/null
+++ b/testsuite/synth/issue2169/mul.vhdl
@@ -0,0 +1,17 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity mul is
+	port(
+		a :  in unsigned( 7 downto 0);
+		b :  in unsigned(15 downto 0);
+		r : out unsigned(23 downto 0)
+	);
+end entity;
+
+architecture rtl of mul is
+
+begin
+	r <= resize(a*b, 24);
+end architecture;
diff --git a/testsuite/synth/issue2169/tb.vhdl b/testsuite/synth/issue2169/tb.vhdl
new file mode 100644
index 000000000..d30be60b9
--- /dev/null
+++ b/testsuite/synth/issue2169/tb.vhdl
@@ -0,0 +1,31 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity tb_mul is
+end entity;
+
+architecture tb of tb_mul is
+	signal a : unsigned( 7 downto 0);
+	signal b : unsigned(15 downto 0);
+	signal r : unsigned(23 downto 0);
+begin
+	
+	u0 : entity work.bug
+	port map(
+		a => a,
+		b => b,
+		r => r
+	);
+	
+	process
+	begin
+		a <= to_unsigned(243,8);
+		b <= to_unsigned(34560,16);
+		wait for 1 ns;
+		report integer'image(to_integer(r));
+		assert r = to_unsigned(8398080, 24);
+		wait;
+	end process;
+
+end architecture;
diff --git a/testsuite/synth/issue2169/tb_mul.vhdl b/testsuite/synth/issue2169/tb_mul.vhdl
new file mode 100644
index 000000000..999d1a05f
--- /dev/null
+++ b/testsuite/synth/issue2169/tb_mul.vhdl
@@ -0,0 +1,31 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity tb_mul is
+end entity;
+
+architecture tb of tb_mul is
+	signal a : unsigned( 7 downto 0);
+	signal b : unsigned(15 downto 0);
+	signal r : unsigned(23 downto 0);
+begin
+	
+	u0 : entity work.mul
+	port map(
+		a => a,
+		b => b,
+		r => r
+	);
+	
+	process
+	begin
+		a <= to_unsigned(243,8);
+		b <= to_unsigned(34560,16);
+		wait for 1 ns;
+		report integer'image(to_integer(r));
+		assert r = to_unsigned(8398080, 24);
+		wait;
+	end process;
+
+end architecture;
diff --git a/testsuite/synth/issue2169/testsuite.sh b/testsuite/synth/issue2169/testsuite.sh
new file mode 100755
index 000000000..7ebdd2eb9
--- /dev/null
+++ b/testsuite/synth/issue2169/testsuite.sh
@@ -0,0 +1,7 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth_tb mul
+
+echo "Test successful"
-- 
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