From b2b8a8f6c3389ca2764fa22149e68b9b1faae6a6 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Thu, 15 Aug 2019 05:39:58 +0200 Subject: testsuite/synth: fix assert1 assertion. --- testsuite/synth/psl01/assert1.vhdl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'testsuite/synth') diff --git a/testsuite/synth/psl01/assert1.vhdl b/testsuite/synth/psl01/assert1.vhdl index 13e44a1e8..717b4d0f9 100644 --- a/testsuite/synth/psl01/assert1.vhdl +++ b/testsuite/synth/psl01/assert1.vhdl @@ -23,5 +23,5 @@ begin cnt <= val; --psl default clock is rising_edge(clk); - --psl assert always val /= 5 or rst = '1'; + --psl assert always val /= 5 abort rst; end behav; -- cgit v1.2.3