From 9a9e16ab09872600576421ef81385d4dc39c8261 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Tue, 14 Jun 2022 05:52:33 +0200
Subject: testsuite/synth: add a test for #2054

---
 testsuite/synth/issue2054/flip_flop.vhdl | 16 ++++++++++++++++
 testsuite/synth/issue2054/testsuite.sh   | 11 +++++++++++
 2 files changed, 27 insertions(+)
 create mode 100644 testsuite/synth/issue2054/flip_flop.vhdl
 create mode 100755 testsuite/synth/issue2054/testsuite.sh

(limited to 'testsuite/synth')

diff --git a/testsuite/synth/issue2054/flip_flop.vhdl b/testsuite/synth/issue2054/flip_flop.vhdl
new file mode 100644
index 000000000..a5bbe5d27
--- /dev/null
+++ b/testsuite/synth/issue2054/flip_flop.vhdl
@@ -0,0 +1,16 @@
+library ieee;
+use ieee.numeric_std.all;
+use ieee.std_logic_1164.all;
+
+entity flip_flop is 
+  port (
+         clk : in std_logic;
+         wire : in std_logic;
+         reg : out std_logic
+       );
+end;
+
+architecture a_flip_flop of flip_flop is 
+begin
+  reg <= wire when rising_edge(clk);
+end;
diff --git a/testsuite/synth/issue2054/testsuite.sh b/testsuite/synth/issue2054/testsuite.sh
new file mode 100755
index 000000000..af0825e54
--- /dev/null
+++ b/testsuite/synth/issue2054/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth --out=verilog flip_flop.vhdl -e > syn_flip_flop.v
+
+if grep "input  wire" syn_flip_flop.v; then
+  exit 1
+fi
+
+echo "Test successful"
-- 
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