From 904abc55c0821f85151a8328904f5621e60c8f02 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Mon, 12 Sep 2022 05:11:58 +0200 Subject: testsuite/synth: add tests for succ/pred/leftof/rightof attributes --- testsuite/synth/attr02/leftof01.vhdl | 9 +++++++++ testsuite/synth/attr02/pred01.vhdl | 9 +++++++++ testsuite/synth/attr02/rightof01.vhdl | 9 +++++++++ testsuite/synth/attr02/succ01.vhdl | 9 +++++++++ testsuite/synth/attr02/tb_leftof01.vhdl | 17 +++++++++++++++++ testsuite/synth/attr02/tb_pred01.vhdl | 17 +++++++++++++++++ testsuite/synth/attr02/tb_rightof01.vhdl | 17 +++++++++++++++++ testsuite/synth/attr02/tb_succ01.vhdl | 17 +++++++++++++++++ testsuite/synth/attr02/testsuite.sh | 9 +++++++++ 9 files changed, 113 insertions(+) create mode 100644 testsuite/synth/attr02/leftof01.vhdl create mode 100644 testsuite/synth/attr02/pred01.vhdl create mode 100644 testsuite/synth/attr02/rightof01.vhdl create mode 100644 testsuite/synth/attr02/succ01.vhdl create mode 100644 testsuite/synth/attr02/tb_leftof01.vhdl create mode 100644 testsuite/synth/attr02/tb_pred01.vhdl create mode 100644 testsuite/synth/attr02/tb_rightof01.vhdl create mode 100644 testsuite/synth/attr02/tb_succ01.vhdl create mode 100755 testsuite/synth/attr02/testsuite.sh (limited to 'testsuite/synth') diff --git a/testsuite/synth/attr02/leftof01.vhdl b/testsuite/synth/attr02/leftof01.vhdl new file mode 100644 index 000000000..8683fd134 --- /dev/null +++ b/testsuite/synth/attr02/leftof01.vhdl @@ -0,0 +1,9 @@ +entity leftof01 is + port (i : integer; + o : out integer); +end leftof01; + +architecture behav of leftof01 is +begin + o <= integer'leftof(i); +end behav; diff --git a/testsuite/synth/attr02/pred01.vhdl b/testsuite/synth/attr02/pred01.vhdl new file mode 100644 index 000000000..eda38a116 --- /dev/null +++ b/testsuite/synth/attr02/pred01.vhdl @@ -0,0 +1,9 @@ +entity pred01 is + port (i : integer; + o : out integer); +end pred01; + +architecture behav of pred01 is +begin + o <= integer'pred(i); +end behav; diff --git a/testsuite/synth/attr02/rightof01.vhdl b/testsuite/synth/attr02/rightof01.vhdl new file mode 100644 index 000000000..6b0425259 --- /dev/null +++ b/testsuite/synth/attr02/rightof01.vhdl @@ -0,0 +1,9 @@ +entity rightof01 is + port (i : integer; + o : out integer); +end rightof01; + +architecture behav of rightof01 is +begin + o <= integer'rightof(i); +end behav; diff --git a/testsuite/synth/attr02/succ01.vhdl b/testsuite/synth/attr02/succ01.vhdl new file mode 100644 index 000000000..462b2539a --- /dev/null +++ b/testsuite/synth/attr02/succ01.vhdl @@ -0,0 +1,9 @@ +entity succ01 is + port (i : integer; + o : out integer); +end succ01; + +architecture behav of succ01 is +begin + o <= integer'succ(i); +end behav; diff --git a/testsuite/synth/attr02/tb_leftof01.vhdl b/testsuite/synth/attr02/tb_leftof01.vhdl new file mode 100644 index 000000000..b638b347b --- /dev/null +++ b/testsuite/synth/attr02/tb_leftof01.vhdl @@ -0,0 +1,17 @@ +entity tb_leftof01 is +end tb_leftof01; + +architecture behav of tb_leftof01 is + signal i, o : integer := 9; +begin + dut: entity work.leftof01 + port map (i, o); + + process + begin + i <= 5; + wait for 1 ns; + assert o = 4 severity failure; + wait; + end process; +end behav; diff --git a/testsuite/synth/attr02/tb_pred01.vhdl b/testsuite/synth/attr02/tb_pred01.vhdl new file mode 100644 index 000000000..4b60b30ec --- /dev/null +++ b/testsuite/synth/attr02/tb_pred01.vhdl @@ -0,0 +1,17 @@ +entity tb_pred01 is +end tb_pred01; + +architecture behav of tb_pred01 is + signal i, o : integer := 9; +begin + dut: entity work.pred01 + port map (i, o); + + process + begin + i <= 5; + wait for 1 ns; + assert o = 4 severity failure; + wait; + end process; +end behav; diff --git a/testsuite/synth/attr02/tb_rightof01.vhdl b/testsuite/synth/attr02/tb_rightof01.vhdl new file mode 100644 index 000000000..40c567678 --- /dev/null +++ b/testsuite/synth/attr02/tb_rightof01.vhdl @@ -0,0 +1,17 @@ +entity tb_rightof01 is +end tb_rightof01; + +architecture behav of tb_rightof01 is + signal i, o : integer := 9; +begin + dut: entity work.rightof01 + port map (i, o); + + process + begin + i <= 5; + wait for 1 ns; + assert o = 6 severity failure; + wait; + end process; +end behav; diff --git a/testsuite/synth/attr02/tb_succ01.vhdl b/testsuite/synth/attr02/tb_succ01.vhdl new file mode 100644 index 000000000..8ff2d31dc --- /dev/null +++ b/testsuite/synth/attr02/tb_succ01.vhdl @@ -0,0 +1,17 @@ +entity tb_succ01 is +end tb_succ01; + +architecture behav of tb_succ01 is + signal i, o : integer; +begin + dut: entity work.succ01 + port map (i, o); + + process + begin + i <= 5; + wait for 1 ns; + assert o = 6 severity failure; + wait; + end process; +end behav; diff --git a/testsuite/synth/attr02/testsuite.sh b/testsuite/synth/attr02/testsuite.sh new file mode 100755 index 000000000..915c346c0 --- /dev/null +++ b/testsuite/synth/attr02/testsuite.sh @@ -0,0 +1,9 @@ +#! /bin/sh + +. ../../testenv.sh + +for t in succ01 pred01 leftof01 rightof01; do + synth_tb $t +done + +echo "Test successful" -- cgit v1.2.3