From 8ed352778368cfbff239bb2a89fc6a937c65fc26 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sun, 20 Dec 2020 08:52:40 +0100
Subject: testsuite/synth: add tests for #1540

---
 testsuite/synth/issue1540/ent1.vhdl    | 13 +++++++++++++
 testsuite/synth/issue1540/ent2.vhdl    | 14 ++++++++++++++
 testsuite/synth/issue1540/testsuite.sh | 11 +++++++++++
 3 files changed, 38 insertions(+)
 create mode 100644 testsuite/synth/issue1540/ent1.vhdl
 create mode 100644 testsuite/synth/issue1540/ent2.vhdl
 create mode 100755 testsuite/synth/issue1540/testsuite.sh

(limited to 'testsuite/synth')

diff --git a/testsuite/synth/issue1540/ent1.vhdl b/testsuite/synth/issue1540/ent1.vhdl
new file mode 100644
index 000000000..254f6014f
--- /dev/null
+++ b/testsuite/synth/issue1540/ent1.vhdl
@@ -0,0 +1,13 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ent1 is
+    port (
+        o: out bit
+    );
+end entity;
+
+architecture arch of ent1 is
+begin
+    o <= to_bit(std_ulogic' ('L'));
+end architecture;
diff --git a/testsuite/synth/issue1540/ent2.vhdl b/testsuite/synth/issue1540/ent2.vhdl
new file mode 100644
index 000000000..f3fd57f5f
--- /dev/null
+++ b/testsuite/synth/issue1540/ent2.vhdl
@@ -0,0 +1,14 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ent2 is
+    port (
+        o: out bit_vector(3 downto 0)
+    );
+end entity;
+
+architecture arch of ent2 is
+begin
+    o <= to_bitvector(std_ulogic_vector'("01LH"));
+end architecture;
+
diff --git a/testsuite/synth/issue1540/testsuite.sh b/testsuite/synth/issue1540/testsuite.sh
new file mode 100755
index 000000000..a7846d914
--- /dev/null
+++ b/testsuite/synth/issue1540/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for f in ent1 ent2 ; do
+  synth_analyze $f
+done
+
+clean
+
+echo "Test successful"
-- 
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