From 807ee04eb8f01034109fba4e37b955521db27099 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Wed, 15 Jan 2020 06:39:20 +0100
Subject: testsuite/synth: add a test for #1095

---
 testsuite/synth/issue1095/testsuite.sh |  8 +++++
 testsuite/synth/issue1095/top.vhdl     | 62 ++++++++++++++++++++++++++++++++++
 2 files changed, 70 insertions(+)
 create mode 100755 testsuite/synth/issue1095/testsuite.sh
 create mode 100644 testsuite/synth/issue1095/top.vhdl

(limited to 'testsuite/synth')

diff --git a/testsuite/synth/issue1095/testsuite.sh b/testsuite/synth/issue1095/testsuite.sh
new file mode 100755
index 000000000..cae496e7d
--- /dev/null
+++ b/testsuite/synth/issue1095/testsuite.sh
@@ -0,0 +1,8 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=--std=08
+synth top.vhdl -e conf > syn_conf.vhdl
+
+echo "Test successful"
diff --git a/testsuite/synth/issue1095/top.vhdl b/testsuite/synth/issue1095/top.vhdl
new file mode 100644
index 000000000..89405084a
--- /dev/null
+++ b/testsuite/synth/issue1095/top.vhdl
@@ -0,0 +1,62 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity xor_gate is
+	generic (
+		INVERT : boolean
+	);
+	port (
+		a : in std_logic;
+		b : in std_logic;
+		q : out std_logic
+	);
+end;
+
+architecture a of xor_gate is
+begin
+	gen: if INVERT generate
+		q <= not (a xor b);
+	else generate
+		q <= a xor b;
+	end generate;
+end;
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity top is
+	port (
+		x : in std_logic;
+		y : in std_logic;
+		o_custom : out std_logic;
+		o_and : out std_logic
+	);
+end;
+
+architecture a of top is
+	component comp is
+		port (
+			a : in std_logic;
+			b : in std_logic;
+			q : out std_logic
+		);
+	end component;
+begin
+	comp_inst: comp
+		port map (
+			a => x,
+			b => y,
+			q => o_custom
+		);
+
+	o_and <= x and y;
+end;
+configuration conf of top is
+	for a
+		for comp_inst : comp
+			use entity work.xor_gate
+				generic map (
+					INVERT => false
+				);
+		end for;
+	end for;
+end configuration;
-- 
cgit v1.2.3