From 7ba58651202e21fc17dd5d669625a2056bcb83ce Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Wed, 2 Oct 2019 03:35:46 +0200
Subject: testsuite/synth: add synth48

---
 testsuite/synth/synth48/test.vhdl    | 21 +++++++++++++++++++++
 testsuite/synth/synth48/testsuite.sh | 13 +++++++++++++
 2 files changed, 34 insertions(+)
 create mode 100644 testsuite/synth/synth48/test.vhdl
 create mode 100755 testsuite/synth/synth48/testsuite.sh

(limited to 'testsuite/synth')

diff --git a/testsuite/synth/synth48/test.vhdl b/testsuite/synth/synth48/test.vhdl
new file mode 100644
index 000000000..d04d6673f
--- /dev/null
+++ b/testsuite/synth/synth48/test.vhdl
@@ -0,0 +1,21 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+entity test is
+  port (
+    Reset_n_i    : in  std_logic;
+    Clk_i        : in  std_logic
+  );
+end entity test;
+
+
+architecture beh of test is
+begin
+
+  default clock is rising_edge(Clk_i);
+  restrict {Reset_n_i = '0'[*5]; Reset_n_i = '1'[+]}[*1];
+
+end architecture beh;
+
diff --git a/testsuite/synth/synth48/testsuite.sh b/testsuite/synth/synth48/testsuite.sh
new file mode 100755
index 000000000..75c10b387
--- /dev/null
+++ b/testsuite/synth/synth48/testsuite.sh
@@ -0,0 +1,13 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=--std=08
+
+for f in test; do
+  synth $f.vhdl -e $f > syn_$f.vhdl
+  analyze syn_$f.vhdl
+done
+clean
+
+echo "Test successful"
-- 
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