From 55faf476ebc08240e9052d184221b57092e68db9 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sun, 2 Feb 2020 19:38:39 +0100
Subject: testsuite/synth: add test for #1117

---
 testsuite/synth/issue1117/ent.vhdl     | 16 ++++++++++++++++
 testsuite/synth/issue1117/tb_ent.vhdl  | 22 ++++++++++++++++++++++
 testsuite/synth/issue1117/testsuite.sh | 16 ++++++++++++++++
 3 files changed, 54 insertions(+)
 create mode 100644 testsuite/synth/issue1117/ent.vhdl
 create mode 100644 testsuite/synth/issue1117/tb_ent.vhdl
 create mode 100755 testsuite/synth/issue1117/testsuite.sh

(limited to 'testsuite/synth')

diff --git a/testsuite/synth/issue1117/ent.vhdl b/testsuite/synth/issue1117/ent.vhdl
new file mode 100644
index 000000000..135d2d31c
--- /dev/null
+++ b/testsuite/synth/issue1117/ent.vhdl
@@ -0,0 +1,16 @@
+library ieee;
+use ieee.numeric_std.all;
+use ieee.std_logic_1164.all;
+
+entity ent is
+	generic (
+		G : unsigned(31 downto 0)
+	);
+        port (
+          res : out unsigned (31 downto 0));
+end;
+
+architecture a of ent is
+begin
+  res <= g;
+end;
diff --git a/testsuite/synth/issue1117/tb_ent.vhdl b/testsuite/synth/issue1117/tb_ent.vhdl
new file mode 100644
index 000000000..bed2308cc
--- /dev/null
+++ b/testsuite/synth/issue1117/tb_ent.vhdl
@@ -0,0 +1,22 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity tb_ent is
+end;
+
+architecture behav of tb_ent is
+  signal r : unsigned (31 downto 0);
+begin
+  dut: entity work.ent
+    generic map (g => x"ffff_0001")
+    port map (res => r);
+
+  process
+  begin
+    wait for 1 ns;
+    assert r = x"ffff0001" severity failure;
+    wait;
+  end process;
+end behav;
+
diff --git a/testsuite/synth/issue1117/testsuite.sh b/testsuite/synth/issue1117/testsuite.sh
new file mode 100755
index 000000000..7b5a2cb7c
--- /dev/null
+++ b/testsuite/synth/issue1117/testsuite.sh
@@ -0,0 +1,16 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in ent; do
+    analyze $t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+
+    synth '-gg=x"ff_ff_00_01"' $t.vhdl -e $t > syn_$t.vhdl
+    analyze syn_$t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t --ieee-asserts=disable-at-0
+    clean
+done
+
+echo "Test successful"
-- 
cgit v1.2.3