From f9102057180443575edcebe71edb6c3eb1fc571d Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Sun, 3 Nov 2019 07:40:18 +0100 Subject: testsuite/synth/var01: add more tests. --- testsuite/synth/var01/var01c.vhdl | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 testsuite/synth/var01/var01c.vhdl (limited to 'testsuite/synth/var01/var01c.vhdl') diff --git a/testsuite/synth/var01/var01c.vhdl b/testsuite/synth/var01/var01c.vhdl new file mode 100644 index 000000000..35f688c6b --- /dev/null +++ b/testsuite/synth/var01/var01c.vhdl @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity var01c is + port (clk : std_logic; + mask : std_logic_vector (1 downto 0); + val : std_logic_vector (1 downto 0); + res : out std_logic_vector (3 downto 0)); +end var01c; + +architecture behav of var01c is +begin + process (clk) + variable hi, lo : natural; + begin + if rising_edge (clk) then + for i in 0 to 1 loop + if mask (i) = '1' then + lo := i * 2; + hi := lo + 1; + res (hi downto lo) <= val; + end if; + end loop; + end if; + end process; +end behav; -- cgit v1.2.3