From de899bb8cb6e2f43a3e80a6a273d6a459b08e401 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Tue, 17 Sep 2019 02:18:41 +0200
Subject: testsuite/synth: add var01

---
 testsuite/synth/var01/tb_var01.vhdl | 51 +++++++++++++++++++++++++++++++++++++
 1 file changed, 51 insertions(+)
 create mode 100644 testsuite/synth/var01/tb_var01.vhdl

(limited to 'testsuite/synth/var01/tb_var01.vhdl')

diff --git a/testsuite/synth/var01/tb_var01.vhdl b/testsuite/synth/var01/tb_var01.vhdl
new file mode 100644
index 000000000..48dca33a3
--- /dev/null
+++ b/testsuite/synth/var01/tb_var01.vhdl
@@ -0,0 +1,51 @@
+entity tb_var01 is
+end tb_var01;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_var01 is
+  signal clk : std_logic;
+  signal mask : std_logic_vector (3 downto 0);
+  signal val : std_logic_vector (31 downto 0);
+  signal res : std_logic_vector (31 downto 0);
+begin
+  dut: entity work.var01
+    port map (
+      clk => clk,
+      mask => mask,
+      val => val,
+      res => res);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    mask <= x"f";
+    val <= x"12_34_56_78";
+    pulse;
+    assert res = x"12_34_56_78" severity failure;
+    
+    mask <= x"8";
+    val <= x"9a_00_00_00";
+    pulse;
+    assert res = x"9a_34_56_78" severity failure;
+
+    mask <= x"0";
+    val <= x"00_00_00_00";
+    pulse;
+    assert res = x"9a_34_56_78" severity failure;
+
+    mask <= x"5";
+    val <= x"00_bc_00_de";
+    pulse;
+    assert res = x"9a_bc_56_de" severity failure;
+
+    wait;
+  end process;
+end behav;
-- 
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