From 2170c6f1592156b51254f30e2c4d0019fc91855b Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sun, 3 Nov 2019 07:42:21 +0100
Subject: testsuite/synth: add test for tgingold/ghdlsynth-beta#56

---
 testsuite/synth/synth56/test2.vhdl | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)
 create mode 100644 testsuite/synth/synth56/test2.vhdl

(limited to 'testsuite/synth/synth56/test2.vhdl')

diff --git a/testsuite/synth/synth56/test2.vhdl b/testsuite/synth/synth56/test2.vhdl
new file mode 100644
index 000000000..09c82d189
--- /dev/null
+++ b/testsuite/synth/synth56/test2.vhdl
@@ -0,0 +1,16 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity test2 is
+    port (
+        d_in: in std_logic_vector(1 downto 0);
+        d_out: out std_logic_vector(1 downto 0)
+        );
+end entity test2;
+
+architecture rtl of test2 is
+    constant c : std_logic_vector (7 downto 0) := "10010000";
+begin
+    d_out <= c(to_integer(unsigned(d_in))+1 downto to_integer(unsigned(d_in)));
+end rtl;
-- 
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