From a18e1503a9896152268705aab21a6ee491756ff7 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Fri, 7 Aug 2020 21:54:09 +0200
Subject: testsuite/synth: add tests for std_logic_unsigned and
 std_logic_signed.

---
 testsuite/synth/snsuns01/scmpeq.vhdl | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)
 create mode 100644 testsuite/synth/snsuns01/scmpeq.vhdl

(limited to 'testsuite/synth/snsuns01/scmpeq.vhdl')

diff --git a/testsuite/synth/snsuns01/scmpeq.vhdl b/testsuite/synth/snsuns01/scmpeq.vhdl
new file mode 100644
index 000000000..d0ef55339
--- /dev/null
+++ b/testsuite/synth/snsuns01/scmpeq.vhdl
@@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmpeq is
+  port (
+    li : integer;
+    ri : integer;
+    l4 : std_logic_vector (3 downto 0);
+    r3 : std_logic_vector (2 downto 0);
+
+    eq_v4v3 : out boolean;
+    eq_v4i  : out boolean;
+    eq_iv3  : out boolean);
+end cmpeq;
+
+library ieee;
+use ieee.std_logic_signed.all;
+
+architecture behav of cmpeq is
+begin
+  eq_v4v3 <= l4 = r3;
+  eq_v4i  <= l4 = ri;
+  eq_iv3  <= li = r3;
+end behav;
-- 
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