From 34101ea4d4359f4b39dc303649a00ea5d748fa1d Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Thu, 27 Feb 2020 08:00:25 +0100 Subject: testsuite/synth: add a simple test for std_logic_arith. --- testsuite/synth/sns01/sns01.vhdl | 19 +++++++++++++++++++ testsuite/synth/sns01/testsuite.sh | 12 ++++++++++++ 2 files changed, 31 insertions(+) create mode 100644 testsuite/synth/sns01/sns01.vhdl create mode 100755 testsuite/synth/sns01/testsuite.sh (limited to 'testsuite/synth/sns01') diff --git a/testsuite/synth/sns01/sns01.vhdl b/testsuite/synth/sns01/sns01.vhdl new file mode 100644 index 000000000..a8f3b7e60 --- /dev/null +++ b/testsuite/synth/sns01/sns01.vhdl @@ -0,0 +1,19 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +entity sns01 is + port (a : natural range 0 to 15; + b : out unsigned (3 downto 0); + clk : std_logic); +end sns01; + +architecture behav of sns01 is +begin + process (clk) + begin + if rising_edge(clk) then + b <= conv_unsigned (a, 4); + end if; + end process; +end behav; diff --git a/testsuite/synth/sns01/testsuite.sh b/testsuite/synth/sns01/testsuite.sh new file mode 100755 index 000000000..2f17c5d8f --- /dev/null +++ b/testsuite/synth/sns01/testsuite.sh @@ -0,0 +1,12 @@ +#! /bin/sh + +. ../../testenv.sh + +GHDL_STD_FLAGS=--ieee=synopsys +for t in sns01; do + synth $t.vhdl -e $t > syn_$t.vhdl +# analyze syn_$t.vhdl + clean +done + +echo "Test successful" -- cgit v1.2.3