From cf9d17b816445b414bf1855bff8bd070ea4da1b6 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Thu, 20 Feb 2020 07:41:18 +0100
Subject: testsuite/synth: add a source for mem01

---
 testsuite/synth/mem01/NOTES.txt   |  2 ++
 testsuite/synth/mem01/sram02.vhdl | 29 +++++++++++++++++++++++++++++
 2 files changed, 31 insertions(+)
 create mode 100644 testsuite/synth/mem01/sram02.vhdl

(limited to 'testsuite/synth/mem01')

diff --git a/testsuite/synth/mem01/NOTES.txt b/testsuite/synth/mem01/NOTES.txt
index 84edd5041..3c362c073 100644
--- a/testsuite/synth/mem01/NOTES.txt
+++ b/testsuite/synth/mem01/NOTES.txt
@@ -3,7 +3,9 @@ Tests for RAMs
 
 rom1: asynchronous ROM
 srom01: Read (initialized ROM).
+
 sram01: Read+Write (at the same address).
+sram02: Write+Read (at the same address).
 dpram1: Read+Write (using signals, without enables)
 dpram2: Read+Write (using a variable, without enables)
 dpram3: Read+Write (like dpram2 but downto)
diff --git a/testsuite/synth/mem01/sram02.vhdl b/testsuite/synth/mem01/sram02.vhdl
new file mode 100644
index 000000000..dc9be662f
--- /dev/null
+++ b/testsuite/synth/mem01/sram02.vhdl
@@ -0,0 +1,29 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity sram02 is
+  port (
+    clk_i  : std_logic;
+    addr_i : std_logic_vector(3 downto 0);
+    data_i : std_logic_vector(7 downto 0);
+    data_o : out std_logic_vector(7 downto 0);
+    wen_i   : std_logic);
+end sram02;
+
+architecture behav of sram02 is
+begin
+  process (clk_i, addr_i)
+    type mem_type is array (0 to 15) of std_logic_vector (7 downto 0);
+    variable mem : mem_type;
+    variable addr : natural range mem_type'range;
+  begin
+    if rising_edge(clk_i) then
+      addr := to_integer (unsigned (addr_i));
+      if wen_i = '1' then
+        mem (addr) := data_i;
+      end if;
+      data_o <= mem (addr);
+    end if;
+  end process;
+end behav;
-- 
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