From 7dadb10612db2ba3d8507c59ed3491fc810e91c9 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Tue, 1 Oct 2019 06:10:29 +0200
Subject: testsuite/synth: add testcase for #955

---
 testsuite/synth/issue955/ent1.vhdl | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)
 create mode 100644 testsuite/synth/issue955/ent1.vhdl

(limited to 'testsuite/synth/issue955/ent1.vhdl')

diff --git a/testsuite/synth/issue955/ent1.vhdl b/testsuite/synth/issue955/ent1.vhdl
new file mode 100644
index 000000000..68c0f9c06
--- /dev/null
+++ b/testsuite/synth/issue955/ent1.vhdl
@@ -0,0 +1,25 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ent1 is
+    port (
+        clk : in std_logic;
+        o : out std_logic_vector (0 to 7)
+    );
+end ent1;
+
+architecture a of ent1 is
+    type reg_t is array(0 to 7) of std_logic_vector(0 to 7);
+
+    signal reg : reg_t := (x"10", x"11", x"12", x"13",
+                           x"14", x"15", x"16", x"17");
+begin
+    process(clk)
+    begin
+        if rising_edge(clk) then
+            reg <= reg(1 to 7) & x"00";
+        end if;
+    end process;
+
+    o <= reg (0);
+end;
-- 
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