From ea460cb31034202c6d6d3fd720126fd0bedd8820 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Tue, 14 Mar 2023 08:18:13 +0100 Subject: testsuite/synth: add a test for #2390 --- testsuite/synth/issue2390/ram.vhdl | 28 ++++++++++++++++++++++ testsuite/synth/issue2390/rom.vhdl | 21 +++++++++++++++++ testsuite/synth/issue2390/testsuite.sh | 9 +++++++ testsuite/synth/issue2390/top.vhdl | 29 +++++++++++++++++++++++ testsuite/synth/issue2390/types.vhdl | 9 +++++++ testsuite/synth/issue2390/ucpu.vhdl | 43 ++++++++++++++++++++++++++++++++++ 6 files changed, 139 insertions(+) create mode 100644 testsuite/synth/issue2390/ram.vhdl create mode 100644 testsuite/synth/issue2390/rom.vhdl create mode 100755 testsuite/synth/issue2390/testsuite.sh create mode 100644 testsuite/synth/issue2390/top.vhdl create mode 100644 testsuite/synth/issue2390/types.vhdl create mode 100644 testsuite/synth/issue2390/ucpu.vhdl (limited to 'testsuite/synth/issue2390') diff --git a/testsuite/synth/issue2390/ram.vhdl b/testsuite/synth/issue2390/ram.vhdl new file mode 100644 index 000000000..36595fb4d --- /dev/null +++ b/testsuite/synth/issue2390/ram.vhdl @@ -0,0 +1,28 @@ +library ieee; +context ieee.ieee_std_context; +use work.uCPUtypes.all; + +entity RAM is + port ( + clk : in logic; + abus : in unsigned_byte; + dbus : inout unsigned_byte; + wr_en : in logic + ); +end entity RAM; + +architecture RTL of RAM is + type memory is array (0 to 255) of unsigned_byte; + signal mem : memory := (others => x"00"); +begin + +dbus <= mem(to_integer(abus)) when not wr_en else x"ZZ"; + +syn_write: process (clk) +begin + if rising_edge(clk) then + mem(to_integer(abus)) <= dbus when wr_en else unaffected; + end if; +end process syn_write; + +end architecture RTL; diff --git a/testsuite/synth/issue2390/rom.vhdl b/testsuite/synth/issue2390/rom.vhdl new file mode 100644 index 000000000..07c068ebf --- /dev/null +++ b/testsuite/synth/issue2390/rom.vhdl @@ -0,0 +1,21 @@ +library ieee; +context ieee.ieee_std_context; +use work.uCPUtypes.all; + +entity ROM is + port ( + abus : in unsigned_byte; + dbus : out code_word; + en : in logic + ); +end entity ROM; + +architecture RTL of ROM is + type memory is array (0 to 255) of code_word; + constant mem : memory := (x"777", others => x"000"); +begin + +dbus <= mem(to_integer(abus)) when en else x"ZZZ"; + +end architecture RTL; + diff --git a/testsuite/synth/issue2390/testsuite.sh b/testsuite/synth/issue2390/testsuite.sh new file mode 100755 index 000000000..abb7300fe --- /dev/null +++ b/testsuite/synth/issue2390/testsuite.sh @@ -0,0 +1,9 @@ +#! /bin/sh + +. ../../testenv.sh + +GHDL_STD_FLAGS=--std=08 + +synth types.vhdl top.vhdl ram.vhdl ucpu.vhdl rom.vhdl -e > syn_top.vhdl + +echo "Test successful" diff --git a/testsuite/synth/issue2390/top.vhdl b/testsuite/synth/issue2390/top.vhdl new file mode 100644 index 000000000..5c08f590c --- /dev/null +++ b/testsuite/synth/issue2390/top.vhdl @@ -0,0 +1,29 @@ +library ieee; +context ieee.ieee_std_context; +use work.uCPUtypes.all; + +entity top is + port ( + rst, clk : in logic; + display : out unsigned_byte; + stb : out logic + ); +end entity top; + +architecture mixed of top is + signal rom_addr, ram_addr, ram_data : unsigned_byte; + signal rom_data : code_word; + signal wr_en : logic; +begin + +stb <= '1' when wr_en = '1' and ram_addr = x"00" else '0'; + +display <= ram_data; + +CPU_instance: entity work.uCPU(RTL) port map (rst, clk, rom_addr, rom_data, ram_addr, ram_data, wr_en); + +ROM_instance: entity work.ROM(RTL) port map (rom_addr, rom_data, '1'); + +RAM_instance: entity work.RAM(RTL) port map (clk, ram_addr, ram_data, wr_en); + +end architecture mixed; diff --git a/testsuite/synth/issue2390/types.vhdl b/testsuite/synth/issue2390/types.vhdl new file mode 100644 index 000000000..7d751e79a --- /dev/null +++ b/testsuite/synth/issue2390/types.vhdl @@ -0,0 +1,9 @@ +library ieee; +context ieee.ieee_std_context; + +package uCPUtypes is + alias logic is std_ulogic; + alias logic_vec is std_ulogic_vector; + subtype unsigned_byte is unsigned(7 downto 0); + subtype code_word is unsigned(11 downto 0); +end package uCPUtypes; diff --git a/testsuite/synth/issue2390/ucpu.vhdl b/testsuite/synth/issue2390/ucpu.vhdl new file mode 100644 index 000000000..7bcc938e2 --- /dev/null +++ b/testsuite/synth/issue2390/ucpu.vhdl @@ -0,0 +1,43 @@ +library ieee; +context ieee.ieee_std_context; +use work.uCPUtypes.all; + +entity uCPU is + port ( + rst, clk : in logic; + rom_addr : out unsigned_byte; + rom_data : in code_word; + ram_addr : out unsigned_byte; + ram_data : inout unsigned_byte; + wr_en : out logic + ); +end entity uCPU; + +architecture RTL of uCPU is + signal IR : unsigned (3 downto 0); + signal A, PC : unsigned_byte := x"00"; +begin + +rom_addr <= PC; + +ram_addr <= A; + +ram_data <= x"ZZ"; + +wr_en <= '0'; + +process (clk) is +begin + if rising_edge(clk) then + if rst then + PC <= x"00"; + A <= x"00"; + else + IR <= rom_data(11 downto 8); + A <= rom_data(7 downto 0); + PC <= PC + 1; + end if; + end if; +end process; + +end architecture RTL; -- cgit v1.2.3