From 91c892934daa16cd2b1ba65331346f691d98fd69 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sun, 12 Jun 2022 06:09:39 +0200
Subject: testsuite/synth: add a test for #2089

---
 testsuite/synth/issue2089/bug.vhdl     | 42 ++++++++++++++++++++++++++++++++++
 testsuite/synth/issue2089/testsuite.sh |  7 ++++++
 2 files changed, 49 insertions(+)
 create mode 100644 testsuite/synth/issue2089/bug.vhdl
 create mode 100755 testsuite/synth/issue2089/testsuite.sh

(limited to 'testsuite/synth/issue2089')

diff --git a/testsuite/synth/issue2089/bug.vhdl b/testsuite/synth/issue2089/bug.vhdl
new file mode 100644
index 000000000..b36b08786
--- /dev/null
+++ b/testsuite/synth/issue2089/bug.vhdl
@@ -0,0 +1,42 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity bug is
+port(
+    clk : in std_ulogic
+);
+end entity;
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity ent is
+port(
+    data : in std_ulogic_vector
+);
+end entity;
+
+architecture rtl of bug is
+
+    type data_t is record
+        a : std_ulogic;
+        b : std_ulogic;
+    end record;
+
+    function to_sulv(data : data_t) return std_ulogic_vector is
+        constant ret : std_ulogic_vector(1 downto 0) := data.a & data.b;
+    begin
+        return ret;
+    end function;
+
+    constant data : data_t := (a => '0', b => '1');
+begin
+    u0 : entity work.ent 
+    port map(data => to_sulv(data));
+end architecture;
+
+architecture rtl of ent is
+
+begin
+
+end architecture;
diff --git a/testsuite/synth/issue2089/testsuite.sh b/testsuite/synth/issue2089/testsuite.sh
new file mode 100755
index 000000000..6ec49749f
--- /dev/null
+++ b/testsuite/synth/issue2089/testsuite.sh
@@ -0,0 +1,7 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth_only bug
+
+echo "Test successful"
-- 
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