From 9443cb4d447460f592b645c6bc66f73bbee87c1e Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Wed, 25 Jan 2023 08:16:43 +0100
Subject: testsuite/synth: adjust reproducer for #2062

---
 testsuite/synth/issue2062/repro.vhdl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'testsuite/synth/issue2062/repro.vhdl')

diff --git a/testsuite/synth/issue2062/repro.vhdl b/testsuite/synth/issue2062/repro.vhdl
index 2b676415c..9fb8694fa 100644
--- a/testsuite/synth/issue2062/repro.vhdl
+++ b/testsuite/synth/issue2062/repro.vhdl
@@ -3,7 +3,7 @@ use ieee.std_logic_1164.all;
 
 entity repro is port (
    a : in  std_logic_vector(5 downto 0);
-   y : out std_ulogic_vector(3 downto -2));
+   y : out std_ulogic_vector(7 downto 2));
 end entity;
 
 architecture beh of repro is
-- 
cgit v1.2.3