From c6163507c69c9b33188876224a1f615d43a94712 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Tue, 5 Apr 2022 19:15:57 +0200
Subject: testsuite/synth: add tests for #2021

---
 testsuite/synth/issue2021/ent.vhdl     | 19 +++++++++++++++++++
 testsuite/synth/issue2021/repro1.vhdl  | 15 +++++++++++++++
 testsuite/synth/issue2021/repro2.vhdl  | 17 +++++++++++++++++
 testsuite/synth/issue2021/testsuite.sh | 10 ++++++++++
 4 files changed, 61 insertions(+)
 create mode 100644 testsuite/synth/issue2021/ent.vhdl
 create mode 100644 testsuite/synth/issue2021/repro1.vhdl
 create mode 100644 testsuite/synth/issue2021/repro2.vhdl
 create mode 100755 testsuite/synth/issue2021/testsuite.sh

(limited to 'testsuite/synth/issue2021')

diff --git a/testsuite/synth/issue2021/ent.vhdl b/testsuite/synth/issue2021/ent.vhdl
new file mode 100644
index 000000000..71c105feb
--- /dev/null
+++ b/testsuite/synth/issue2021/ent.vhdl
@@ -0,0 +1,19 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity ent is
+end ent;
+
+architecture ent of ent is
+  type my_record is record
+    field_a : std_logic_vector;                           -- Parametrized on instantiation
+    field_b : std_logic_vector(31 downto 0); -- Width set by generic
+  end record;
+
+  signal bar : my_record(field_a(7 downto 0));
+  signal baz : my_record(field_a(7 downto 0));
+
+begin
+
+end ent;
diff --git a/testsuite/synth/issue2021/repro1.vhdl b/testsuite/synth/issue2021/repro1.vhdl
new file mode 100644
index 000000000..0344f41cd
--- /dev/null
+++ b/testsuite/synth/issue2021/repro1.vhdl
@@ -0,0 +1,15 @@
+entity ent is
+end ent;
+
+architecture ent of ent is
+  type my_record is record
+    field_a : bit_vector;                           -- Parametrized on instantiation
+    field_b : bit_vector(31 downto 0); -- Width set by generic
+  end record;
+
+  signal bar : my_record(field_a(7 downto 0));
+  signal baz : my_record(field_a(7 downto 0));
+
+begin
+
+end ent;
diff --git a/testsuite/synth/issue2021/repro2.vhdl b/testsuite/synth/issue2021/repro2.vhdl
new file mode 100644
index 000000000..5f59f8dcf
--- /dev/null
+++ b/testsuite/synth/issue2021/repro2.vhdl
@@ -0,0 +1,17 @@
+entity repro2 is
+end;
+
+architecture ent of repro2 is
+  type my_record is record
+    field_a : bit_vector;                           -- Parametrized on instantiation
+    field_b : bit_vector;
+  end record;
+
+  subtype my_record1 is my_record (field_b(3 downto 0));
+
+  signal bar : my_record1(field_a(7 downto 0));
+  signal baz : my_record1(field_a(7 downto 0));
+
+begin
+
+end ent;
diff --git a/testsuite/synth/issue2021/testsuite.sh b/testsuite/synth/issue2021/testsuite.sh
new file mode 100755
index 000000000..c6c6c1ddf
--- /dev/null
+++ b/testsuite/synth/issue2021/testsuite.sh
@@ -0,0 +1,10 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=--std=08
+synth_only repro1
+synth_only repro2
+synth_only ent
+
+echo "Test successful"
-- 
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