From 2918e833acf7f8652099cc290f465b79ad747df2 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Wed, 6 Apr 2022 08:19:38 +0200 Subject: testsuite/synth: add tests for #2019 --- testsuite/synth/issue2019/ent.vhdl | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 testsuite/synth/issue2019/ent.vhdl (limited to 'testsuite/synth/issue2019/ent.vhdl') diff --git a/testsuite/synth/issue2019/ent.vhdl b/testsuite/synth/issue2019/ent.vhdl new file mode 100644 index 000000000..fe4c17bf5 --- /dev/null +++ b/testsuite/synth/issue2019/ent.vhdl @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity ent is + port (p : out std_ulogic_vector(3 downto 0)); + type my_logic_vector is array (natural range <>) of std_ulogic; + + function to_stdlogic (value : std_ulogic) return std_ulogic is + begin + return '0'; + end function; + + function to_stdlogic (value : my_logic_vector) return std_ulogic_vector is + variable tmp : std_ulogic_vector(value'range); + begin + tmp(0) := to_stdlogic(value(0)); + --return tmp; -- uncommenting fixes it + end function; + + signal s : my_logic_vector(3 downto 0); +end entity; + +architecture a of ent is +begin + p <= to_stdlogic(s); +end architecture; -- cgit v1.2.3