From 4c0f9967e541b914a207bd4419d62d00d3e1745c Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Wed, 16 Jun 2021 07:48:22 +0200 Subject: testsuite/synth: add test for #1781 --- testsuite/synth/issue1781/simple2_dc.vhdl | 34 +++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 testsuite/synth/issue1781/simple2_dc.vhdl (limited to 'testsuite/synth/issue1781/simple2_dc.vhdl') diff --git a/testsuite/synth/issue1781/simple2_dc.vhdl b/testsuite/synth/issue1781/simple2_dc.vhdl new file mode 100644 index 000000000..6bc084577 --- /dev/null +++ b/testsuite/synth/issue1781/simple2_dc.vhdl @@ -0,0 +1,34 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity simple2_dc is + port ( + rclk_i : in std_ulogic; + wclk_i : in std_ulogic; + rden_i : in std_ulogic; + wren_i : in std_ulogic; + addr_i : in std_ulogic_vector(7 downto 0); + data_i : in std_ulogic_vector(15 downto 0); + data_o : out std_ulogic_vector(15 downto 0) + ); +end entity; + +architecture notok of simple2_dc is + type ram_t is array(0 to 2**8-1) of std_ulogic_vector(15 downto 0); +begin + process(wclk_i, rclk_i) + variable memory : ram_t; + begin + if rising_edge(wclk_i) then + if wren_i = '1' then + memory(to_integer(unsigned(addr_i))) := data_i; + end if; + end if; + if rising_edge(rclk_i) then + if rden_i = '1' then + data_o <= memory(to_integer(unsigned(addr_i))); + end if; + end if; + end process; +end architecture; -- cgit v1.2.3