From 092e788d5e00c034593d700859c001a43809038e Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sat, 25 Jul 2020 19:09:58 +0200
Subject: testsuite/synth: add tests for #1406

---
 testsuite/synth/issue1406/half_adder.vhdl | 27 +++++++++++++++++++++++++++
 testsuite/synth/issue1406/repro.vhdl      | 16 ++++++++++++++++
 testsuite/synth/issue1406/repro2.vhdl     | 27 +++++++++++++++++++++++++++
 testsuite/synth/issue1406/testsuite.sh    | 10 ++++++++++
 4 files changed, 80 insertions(+)
 create mode 100644 testsuite/synth/issue1406/half_adder.vhdl
 create mode 100644 testsuite/synth/issue1406/repro.vhdl
 create mode 100644 testsuite/synth/issue1406/repro2.vhdl
 create mode 100755 testsuite/synth/issue1406/testsuite.sh

(limited to 'testsuite/synth/issue1406')

diff --git a/testsuite/synth/issue1406/half_adder.vhdl b/testsuite/synth/issue1406/half_adder.vhdl
new file mode 100644
index 000000000..4a6047ed4
--- /dev/null
+++ b/testsuite/synth/issue1406/half_adder.vhdl
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity half_adder is
+  port (
+    clk_in   : in  std_logic;
+    n_rst_in : in  std_logic;
+    a_in     : in  std_logic;
+    b_in     : in  std_logic;
+    c_out    : out std_logic;
+    s_out    : out std_logic
+    );
+end half_adder;
+
+architecture rtl of half_adder is
+begin
+  reg_proc : process(clk_in, n_rst_in)
+  begin
+    if n_rst_in = '0' then
+      c_out <= '0';
+      s_out <= '0';
+    elsif rising_edge(clk_in) then
+      c_out <= a_in and b_in;
+      s_out <= a_in xor b_in;
+    end if;
+  end process reg_proc;
+end rtl;
diff --git a/testsuite/synth/issue1406/repro.vhdl b/testsuite/synth/issue1406/repro.vhdl
new file mode 100644
index 000000000..a56d9f934
--- /dev/null
+++ b/testsuite/synth/issue1406/repro.vhdl
@@ -0,0 +1,16 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity repro is
+  port (a, b : natural range 0 to 3;
+        o : out std_ulogic);
+end;
+
+architecture behav of repro is
+  type table_2d is array (0 to 3, 0 to 3) of std_ulogic;
+
+  constant table : table_2d := ("0011", "1100", "0101", "1010");
+begin
+  o <= table(a,b);
+end;
+
diff --git a/testsuite/synth/issue1406/repro2.vhdl b/testsuite/synth/issue1406/repro2.vhdl
new file mode 100644
index 000000000..4f5f95b61
--- /dev/null
+++ b/testsuite/synth/issue1406/repro2.vhdl
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity repro is
+  port (a, b : std_ulogic;
+        o : out std_ulogic);
+end;
+
+architecture behav of repro is
+  type table_2d is array (std_ulogic, std_ulogic) of std_ulogic;
+
+  constant and_table : table_2d :=
+  --  UX01ZWLH-
+    ("UU0UUU0UU",   -- U
+     "UX0XXX0XX",   -- X
+     "000000000",   -- 0
+     "UX01XX01X",   -- 1
+     "UX0XXX0XX",   -- Z
+     "UX0XXX0XX",   -- W
+     "000000000",   -- L
+     "UX01XX01X",   -- H
+     "UX0XXX0XX"    -- -
+     );
+begin
+  o <= and_table(a,b);
+end;
+
diff --git a/testsuite/synth/issue1406/testsuite.sh b/testsuite/synth/issue1406/testsuite.sh
new file mode 100755
index 000000000..f6c5c5f5d
--- /dev/null
+++ b/testsuite/synth/issue1406/testsuite.sh
@@ -0,0 +1,10 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth_analyze half_adder
+synth_analyze repro
+
+clean
+
+echo "Test successful"
-- 
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