From bb3c706a8e91e3466983fc48e9473127c75f5970 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Mon, 20 Apr 2020 07:34:31 +0200
Subject: testsuite/synth: add test for #1250

---
 testsuite/synth/issue1250/theunit.vhdl | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)
 create mode 100644 testsuite/synth/issue1250/theunit.vhdl

(limited to 'testsuite/synth/issue1250/theunit.vhdl')

diff --git a/testsuite/synth/issue1250/theunit.vhdl b/testsuite/synth/issue1250/theunit.vhdl
new file mode 100644
index 000000000..177c57507
--- /dev/null
+++ b/testsuite/synth/issue1250/theunit.vhdl
@@ -0,0 +1,28 @@
+library ieee;
+use ieee.std_logic_1164.all;
+entity theunit is
+  port (dout : out std_ulogic);
+end;
+
+architecture rtl of theunit is
+  subtype thenum_t is integer range 0 to 1;
+  type rec_t is record
+    -- NOTE: changing order of these members prevents crash
+    data0 : std_ulogic;
+    bankm : std_ulogic_vector(thenum_t);
+  end record;
+  signal r : rec_t;
+begin
+  thecomb : process(r)
+    variable v      : rec_t;
+    variable thenum : thenum_t := 1;
+  begin
+    v.data0 := '1';
+    v.bankm := (others => '1');
+    -- NOTE: removing any of the lines below prevents crash
+    v.bankm(thenum) := '0';
+    r <= v;
+    dout <= r.data0;
+  end process;
+end;
+
-- 
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