From 562a6eea44012b889dd7bfc97d7a4385d36b8157 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Tue, 14 Apr 2020 08:20:10 +0200 Subject: testsuite/synth: add a test for #1225 --- testsuite/synth/issue1225/tb_top.vhdl | 50 ++++++++++++++++++++++++++++++++++ testsuite/synth/issue1225/testsuite.sh | 7 +++++ testsuite/synth/issue1225/top.vhdl | 30 ++++++++++++++++++++ 3 files changed, 87 insertions(+) create mode 100644 testsuite/synth/issue1225/tb_top.vhdl create mode 100755 testsuite/synth/issue1225/testsuite.sh create mode 100644 testsuite/synth/issue1225/top.vhdl (limited to 'testsuite/synth/issue1225') diff --git a/testsuite/synth/issue1225/tb_top.vhdl b/testsuite/synth/issue1225/tb_top.vhdl new file mode 100644 index 000000000..13666fee5 --- /dev/null +++ b/testsuite/synth/issue1225/tb_top.vhdl @@ -0,0 +1,50 @@ +entity tb_top is +end tb_top; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_top is + signal clk : std_logic; + signal en : std_logic; + signal a, b : std_logic; + signal p, q : std_logic; +begin + dut: entity work.top + port map (clk, en, a, b, p, q); + + process + procedure pulse is + begin + wait for 1 ns; + clk <= '1'; + wait for 1 ns; + clk <= '0'; + end pulse; + begin + clk <= '0'; + + a <= '1'; + b <= '0'; + en <= '0'; + pulse; + assert p = '0' severity failure; + assert q = '0' severity failure; + + a <= '1'; + b <= '1'; + en <= '0'; + pulse; + assert p = '0' severity failure; + assert q = '1' severity failure; + + a <= '1'; + b <= '1'; + en <= '1'; + pulse; + assert p = '1' severity failure; + assert q = '1' severity failure; + + wait; + end process; +end behav; diff --git a/testsuite/synth/issue1225/testsuite.sh b/testsuite/synth/issue1225/testsuite.sh new file mode 100755 index 000000000..60399a753 --- /dev/null +++ b/testsuite/synth/issue1225/testsuite.sh @@ -0,0 +1,7 @@ +#! /bin/sh + +. ../../testenv.sh + +synth_tb top + +echo "Test successful" diff --git a/testsuite/synth/issue1225/top.vhdl b/testsuite/synth/issue1225/top.vhdl new file mode 100644 index 000000000..d114c872a --- /dev/null +++ b/testsuite/synth/issue1225/top.vhdl @@ -0,0 +1,30 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity top is + port ( + clk, en : in std_logic; + a, b : in std_logic; + p, q : out std_logic + ); +end entity; + +architecture arch of top is +begin + process (clk, en, a) + variable tmp : std_logic; + begin + if en = '1' then + tmp := a; + p <= tmp; + else + p <= '0'; + end if; + + if rising_edge(clk) then + tmp := b; + q <= tmp; + end if; + end process; +end architecture; -- cgit v1.2.3