From 121afa1acb074c797d516077092f6903f8cc537e Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Mon, 4 Nov 2019 21:06:51 +0100
Subject: testsuite/synth: add testcase for #1002.

---
 testsuite/synth/issue1002/test.vhdl    | 15 +++++++++++++++
 testsuite/synth/issue1002/testsuite.sh | 11 +++++++++++
 2 files changed, 26 insertions(+)
 create mode 100644 testsuite/synth/issue1002/test.vhdl
 create mode 100755 testsuite/synth/issue1002/testsuite.sh

(limited to 'testsuite/synth/issue1002')

diff --git a/testsuite/synth/issue1002/test.vhdl b/testsuite/synth/issue1002/test.vhdl
new file mode 100644
index 000000000..0e8750807
--- /dev/null
+++ b/testsuite/synth/issue1002/test.vhdl
@@ -0,0 +1,15 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.math_real.all;
+
+entity test is
+    generic (
+        BITS : positive := 2
+        );
+end entity test;
+
+architecture rtl of test is
+    constant count : positive := 2 ** BITS - 1;
+    subtype node_t is integer range 0 to count;
+begin
+end;
diff --git a/testsuite/synth/issue1002/testsuite.sh b/testsuite/synth/issue1002/testsuite.sh
new file mode 100755
index 000000000..dc5334e7e
--- /dev/null
+++ b/testsuite/synth/issue1002/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for f in test; do
+  synth $f.vhdl -e $f > syn_$f.vhdl
+  analyze syn_$f.vhdl
+done
+clean
+
+echo "Test successful"
-- 
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