From 7f4ed5db5e0e9c0967000d50a4f3f14e88bf9dd7 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Tue, 29 Jun 2021 14:43:00 +0200 Subject: Renamed '[sS]ubType' to '[sS]ubtype'. --- testsuite/pyunit/Current.vhdl | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'testsuite/pyunit') diff --git a/testsuite/pyunit/Current.vhdl b/testsuite/pyunit/Current.vhdl index 4ac967c15..b2c7aff11 100644 --- a/testsuite/pyunit/Current.vhdl +++ b/testsuite/pyunit/Current.vhdl @@ -107,6 +107,14 @@ package package_1 is clk : std ); end component; + + constant Pointer_1 : List := new List(1 to 1); + constant Pointer_2 : List := new List'(1 => 0); + signal init : std_logic_vector(abs(mssb_idx(GEN)-GEN'right)-1 downto 0); + constant fid : real := +val; + constant ceq11 : std_logic := '1' ?= '1'; + type rt321 is range t3'reverse_range; + type rt321 is range t3'reverse_range(1); end package; package body package_1 is @@ -120,3 +128,7 @@ package body package_1 is F = 1000 mF; end units; end package body; + +vunit vu (component_1) { + +} -- cgit v1.2.3