From b461845ffeb94e902d84c058238fcfcd4074f1a6 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Sat, 29 Aug 2015 08:01:46 +0200 Subject: Rename gnat/bug directories for non-gna bugs to avoid confusion. --- testsuite/gna/bug010/FIFO.vhdl | 69 +++++++++++++ testsuite/gna/bug010/TestFIFO.vhdl | 193 +++++++++++++++++++++++++++++++++++ testsuite/gna/bug010/testsuite.sh | 10 ++ testsuite/gna/bug011/phonybench.vhdl | 59 +++++++++++ testsuite/gna/bug011/testsuite.sh | 12 +++ testsuite/gna/bug012/demo.vhd | 14 +++ testsuite/gna/bug012/testsuite.sh | 10 ++ testsuite/gna/bug014/bug.vhdl | 15 +++ testsuite/gna/bug014/bug2.vhdl | 4 + testsuite/gna/bug014/bug3.vhdl | 7 ++ testsuite/gna/bug014/testsuite.sh | 10 ++ testsuite/gna/bug015/phys.vhdl | 24 +++++ testsuite/gna/bug015/phys2.vhdl | 14 +++ testsuite/gna/bug015/testsuite.sh | 12 +++ testsuite/gna/bug016/pkg.vhdl | 2 + testsuite/gna/bug016/repro.vhdl | 29 ++++++ testsuite/gna/bug016/repro1.vhdl | 28 +++++ testsuite/gna/bug016/repro2.vhdl | 18 ++++ testsuite/gna/bug016/testsuite.sh | 14 +++ testsuite/gna/bug10/FIFO.vhdl | 69 ------------- testsuite/gna/bug10/TestFIFO.vhdl | 193 ----------------------------------- testsuite/gna/bug10/testsuite.sh | 10 -- testsuite/gna/bug11/phonybench.vhdl | 59 ----------- testsuite/gna/bug11/testsuite.sh | 12 --- testsuite/gna/bug12/demo.vhd | 14 --- testsuite/gna/bug12/testsuite.sh | 10 -- testsuite/gna/bug14/bug.vhdl | 15 --- testsuite/gna/bug14/bug2.vhdl | 4 - testsuite/gna/bug14/bug3.vhdl | 7 -- testsuite/gna/bug14/testsuite.sh | 10 -- testsuite/gna/bug15/phys.vhdl | 24 ----- testsuite/gna/bug15/phys2.vhdl | 14 --- testsuite/gna/bug15/testsuite.sh | 12 --- testsuite/gna/bug16/pkg.vhdl | 2 - testsuite/gna/bug16/repro.vhdl | 29 ------ testsuite/gna/bug16/repro1.vhdl | 28 ----- testsuite/gna/bug16/repro2.vhdl | 18 ---- testsuite/gna/bug16/testsuite.sh | 14 --- testsuite/gna/testsuite.sh | 3 +- 39 files changed, 546 insertions(+), 545 deletions(-) create mode 100644 testsuite/gna/bug010/FIFO.vhdl create mode 100644 testsuite/gna/bug010/TestFIFO.vhdl create mode 100755 testsuite/gna/bug010/testsuite.sh create mode 100644 testsuite/gna/bug011/phonybench.vhdl create mode 100755 testsuite/gna/bug011/testsuite.sh create mode 100644 testsuite/gna/bug012/demo.vhd create mode 100755 testsuite/gna/bug012/testsuite.sh create mode 100644 testsuite/gna/bug014/bug.vhdl create mode 100644 testsuite/gna/bug014/bug2.vhdl create mode 100644 testsuite/gna/bug014/bug3.vhdl create mode 100755 testsuite/gna/bug014/testsuite.sh create mode 100644 testsuite/gna/bug015/phys.vhdl create mode 100644 testsuite/gna/bug015/phys2.vhdl create mode 100755 testsuite/gna/bug015/testsuite.sh create mode 100644 testsuite/gna/bug016/pkg.vhdl create mode 100644 testsuite/gna/bug016/repro.vhdl create mode 100644 testsuite/gna/bug016/repro1.vhdl create mode 100644 testsuite/gna/bug016/repro2.vhdl create mode 100755 testsuite/gna/bug016/testsuite.sh delete mode 100644 testsuite/gna/bug10/FIFO.vhdl delete mode 100644 testsuite/gna/bug10/TestFIFO.vhdl delete mode 100755 testsuite/gna/bug10/testsuite.sh delete mode 100644 testsuite/gna/bug11/phonybench.vhdl delete mode 100755 testsuite/gna/bug11/testsuite.sh delete mode 100644 testsuite/gna/bug12/demo.vhd delete mode 100755 testsuite/gna/bug12/testsuite.sh delete mode 100644 testsuite/gna/bug14/bug.vhdl delete mode 100644 testsuite/gna/bug14/bug2.vhdl delete mode 100644 testsuite/gna/bug14/bug3.vhdl delete mode 100755 testsuite/gna/bug14/testsuite.sh delete mode 100644 testsuite/gna/bug15/phys.vhdl delete mode 100644 testsuite/gna/bug15/phys2.vhdl delete mode 100755 testsuite/gna/bug15/testsuite.sh delete mode 100644 testsuite/gna/bug16/pkg.vhdl delete mode 100644 testsuite/gna/bug16/repro.vhdl delete mode 100644 testsuite/gna/bug16/repro1.vhdl delete mode 100644 testsuite/gna/bug16/repro2.vhdl delete mode 100755 testsuite/gna/bug16/testsuite.sh (limited to 'testsuite/gna') diff --git a/testsuite/gna/bug010/FIFO.vhdl b/testsuite/gna/bug010/FIFO.vhdl new file mode 100644 index 000000000..e68a04e55 --- /dev/null +++ b/testsuite/gna/bug010/FIFO.vhdl @@ -0,0 +1,69 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity FIFO is + + generic(Depth : integer := 3); + + port( + iClk : in std_logic; + iReset : in std_logic; + -- write port + iWrEn : in std_logic; + iData : in std_logic_vector(7 downto 0); + oHasSpace : out std_logic; + -- read port + iRdEn : in std_logic; + oData : out std_logic_vector(7 downto 0); + oHasData : out std_logic + ); +end FIFO; + +architecture behaviour of FIFO is + + constant DMSB : integer := Depth - 1; + constant Size : integer := 2 ** DEPTH; + + type regArrayT is array(0 to Size-1) of std_logic_vector(7 downto 0); + + signal free : unsigned(Depth downto 0) := (others => '0'); + signal rIdx, wIdx : unsigned(DMSB downto 0) := (others => '0'); + signal regArray : regArrayT; + signal rdEn, wrEn : std_logic; + signal hasData, hasSpace : std_logic; + +begin + + oData <= regArray(to_integer(rIdx)); + hasData <= '0' when free = Size else '1'; + oHasData <= hasData; + + hasSpace <= '0' when free = to_unsigned(0, Depth) else '1'; + oHasSpace <= hasSpace; + + rdEn <= iRdEn and hasData; + wrEn <= iWrEn and hasSpace; + + main: process(iClk) begin + if iClk'event and iClk = '1' then + if iReset = '1' then + free <= to_unsigned(Size, Depth + 1); + rIdx <= (others => '0'); + wIdx <= (others => '0'); + elsif wrEn = '1' and rdEn = '1' then + rIdx <= rIdx + 1; + regArray(to_integer(wIdx)) <= iData; + wIdx <= wIdx + 1; + elsif rdEn = '1' then + rIdx <= rIdx + 1; + free <= free + 1; + elsif wrEn = '1' then + regArray(to_integer(wIdx)) <= iData; + wIdx <= wIdx + 1; + free <= free - 1; + end if; + end if; + end process; + +end behaviour; diff --git a/testsuite/gna/bug010/TestFIFO.vhdl b/testsuite/gna/bug010/TestFIFO.vhdl new file mode 100644 index 000000000..c033172cd --- /dev/null +++ b/testsuite/gna/bug010/TestFIFO.vhdl @@ -0,0 +1,193 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +-- equal speed writer and reader +-- faster writer +-- faster reader + +entity TestFIFO is +end TestFIFO; + + +architecture behaviour of TestFIFO is + + component FIFO is + generic(Depth : integer := 3); + port( + iClk : in std_logic; + iReset : in std_logic; + -- write port + iWrEn : in std_logic; + iData : in std_logic_vector(7 downto 0); + oHasSpace : out std_logic; + -- read port + iRdEn : in std_logic; + oData : out std_logic_vector(7 downto 0); + oHasData : out std_logic + ); + end component; + + type ramType is array(0 to 255) of std_logic_vector(7 downto 0); + + signal clk, reset : std_logic; + signal wrEn, rdEn : std_logic; + signal inData, outData : std_logic_vector(7 downto 0); + signal hasSpace, hasData : std_logic; + + signal rawInData : std_logic_vector(7 downto 0); + signal rawWrEn, rawRdEn : std_logic; + + signal dstRAM : ramType; + + signal writerData : unsigned(8 downto 0) := (others => '0'); + signal writerWrEn : std_logic; + signal writeDone : std_logic; + signal writerClkCntInit, readerClkCntInit : unsigned(1 downto 0) := "00"; + signal writerClkCnt, readerClkCnt : unsigned(1 downto 0) := "00"; + + signal readerCnt : unsigned(8 downto 0) := (others => '0'); + signal readerRdEn : std_logic; + signal readDone : std_logic; + + signal rawMode : std_logic; + + +begin + + FIFO0: FIFO port map( + iClk => clk, iReset => reset, + iWrEn => wrEn, iData => inData, oHasSpace => hasSpace, + iRdEn => rdEn, oData => outData, oHasData => hasData + ); + + wrEn <= rawWrEn when rawMode = '1' else writerWrEn; + rdEn <= rawRdEn when rawMode = '1' else readerRdEn; + + inData <= rawInData when rawMode = '1' else std_logic_vector(writerData(7 downto 0)); + writeDone <= writerData(7); -- done when writerData == 0x100 + writerWrEn <= '1' when (writerClkCnt = "00") and (hasSpace = '1') and (writeDone = '0') else '0'; + + fifoWriter: process(clk) + begin + if clk'event and clk = '1' and reset = '0' then + if writerClkCnt = "00" then + if hasSpace = '1' and writeDone = '0' then + writerData <= writerData + 1; + end if; + report "writerClkCnt <= writerClkCntInit;"; + writerClkCnt <= writerClkCntInit; + else + report "writerClkCnt <= writerClkCnt - 1;"; + writerClkCnt <= writerClkCnt - 1; + end if; + end if; + end process; + + readDone <= readerCnt(7); -- done when readerCnt == 0x100 + readerRdEn <= '1' when readerClkCnt = "00" and hasData = '1' and readDone = '0' else '0'; + + fifoReader: process(clk) + begin + if clk'event and clk = '1' and reset = '0' then + if readerClkCnt = "00" then + if hasData = '1' and readDone = '0' then + dstRAM(to_integer(readerCnt)) <= outData; + readerCnt <= readerCnt + 1; + end if; + readerClkCnt <= readerClkCntInit; + else + readerClkCnt <= readerClkCnt - 1; + end if; + end if; + end process; + + main: process + + procedure nextCycle is begin + wait for 500 ns; + report "rise"; + clk <= '1'; + wait for 500 ns; + clk <= '0'; + end procedure; + + procedure doReset is begin + reset <= '1'; + clk <= '0'; + nextCycle; + reset <= '0'; + end procedure; + + procedure testSimple is + + procedure write(data : std_logic_vector(7 downto 0); expHasData, expHasSpace: std_logic) is begin + rawWrEn <= '1'; + rawInData <= data; + nextCycle; + assert hasData = expHasData and hasSpace = expHasSpace; + end procedure; + + begin + rawMode <= '1'; + rawWrEn <= '0'; + rawRdEn <= '0'; + doReset; + assert hasData = '0' and hasSpace = '1'; + write(X"70", '1', '1'); + write(X"61", '1', '1'); + write(X"52", '1', '1'); + write(X"43", '1', '1'); + write(X"34", '1', '1'); + write(X"25", '1', '1'); + write(X"16", '1', '1'); + write(X"07", '1', '0'); + write(X"5a", '1', '0'); -- attempt to write to the full FIFO, should be ignored + end procedure; + + procedure clearDst is + variable i : integer; + begin + for i in 0 to 255 loop + dstRAM(i) <= X"00"; + end loop; + end procedure; + + procedure checkDst is + variable i : integer; + begin + for i in 0 to 255 loop + assert dstRAM(i) = std_logic_vector(to_unsigned(i, 8)); + end loop; + end procedure; + + -- 0 means fastest + procedure setWriterSpeed(div: integer) is begin + writerClkCntInit <= to_unsigned(div, 2); + writerClkCnt <= to_unsigned(div, 2); + writerData <= (others => '0'); + end procedure; + + procedure setReaderSpeed(div: integer) is begin + readerClkCntInit <= to_unsigned(div, 2); + readerClkCnt <= to_unsigned(div, 2); + end procedure; + + procedure testEqualFastSpeed is begin + setWriterSpeed(0); + setReaderSpeed(0); + clearDst; + doReset; + while readDone = '0' loop + nextCycle; + end loop; + checkDst; + end procedure; + + begin + testSimple; + -- testEqualFastSpeed; + wait; -- wait forever, end simulation + end process; + +end behaviour; diff --git a/testsuite/gna/bug010/testsuite.sh b/testsuite/gna/bug010/testsuite.sh new file mode 100755 index 000000000..2c649ecef --- /dev/null +++ b/testsuite/gna/bug010/testsuite.sh @@ -0,0 +1,10 @@ +#! /bin/sh + +. ../../testenv.sh + +analyze FIFO.vhdl TestFIFO.vhdl +elab_simulate testfifo --stop-time=4us + +clean + +echo "Test successful" diff --git a/testsuite/gna/bug011/phonybench.vhdl b/testsuite/gna/bug011/phonybench.vhdl new file mode 100644 index 000000000..040980454 --- /dev/null +++ b/testsuite/gna/bug011/phonybench.vhdl @@ -0,0 +1,59 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity phonybench is + generic ( + GENSTR : string := "adrien"; + GENSTDLV : std_logic_vector(5 downto 0) := "111000"; + GENSTDL : std_logic := '1'; + GENNAT : natural := 22 + ); +end phonybench; + +architecture bench of phonybench is + + type char2std_t is array(character) of std_ulogic; + + constant char2std_c : char2std_t := ( + 'U' => 'U', + 'X' => 'X', + '0' => '0', + '1' => '1', + 'Z' => 'Z', + 'W' => 'W', + 'L' => 'L', + 'H' => 'H', + '-' => '-', + others => 'X' + ); + + function str2std(arg : string) return std_logic_vector is + variable result : std_logic_vector(arg'length - 1 downto 0); + variable j : integer; + begin + j := arg'length - 1; + for i in arg'range loop + result(j) := char2std_c(arg(i)); + j := j - 1; + end loop; + return result; + end function; + + signal sigvec1 : std_logic_vector(5 downto 0) := str2std(GENSTR); + signal sigvec2 : std_logic_vector(5 downto 0) := GENSTDLV; + signal siglog : std_logic := GENSTDL; + signal signat : natural := GENNAT; + + signal clk : std_logic := '0'; + +begin + + clk <= not clk after 5 ms; + + sigvec1 <= str2std(GENSTR); + sigvec2 <= GENSTDLV; + siglog <= GENSTDL; + signat <= GENNAT; + +end architecture; diff --git a/testsuite/gna/bug011/testsuite.sh b/testsuite/gna/bug011/testsuite.sh new file mode 100755 index 000000000..5823c99d5 --- /dev/null +++ b/testsuite/gna/bug011/testsuite.sh @@ -0,0 +1,12 @@ +#! /bin/sh + +. ../../testenv.sh + +analyze phonybench.vhdl +elab_simulate phonybench --stop-time=1sec --fst=pb.fst + +rm -f pb.fst pb.ghw + +clean + +echo "Test successful" diff --git a/testsuite/gna/bug012/demo.vhd b/testsuite/gna/bug012/demo.vhd new file mode 100644 index 000000000..2b97782f6 --- /dev/null +++ b/testsuite/gna/bug012/demo.vhd @@ -0,0 +1,14 @@ +entity bar is +end entity bar; +entity \foo\ is + port (test : in bit); +end entity \foo\; +architecture structural of \foo\ is +begin -- architecture structural +end architecture structural; +architecture structural of bar is + signal test : bit; +begin -- architecture structural + foo_1: entity work.\foo\ + port map (test => test); +end architecture structural; diff --git a/testsuite/gna/bug012/testsuite.sh b/testsuite/gna/bug012/testsuite.sh new file mode 100755 index 000000000..9b3d98c20 --- /dev/null +++ b/testsuite/gna/bug012/testsuite.sh @@ -0,0 +1,10 @@ +#! /bin/sh + +. ../../testenv.sh + +analyze demo.vhd +elab_simulate bar structural + +clean + +echo "Test successful" diff --git a/testsuite/gna/bug014/bug.vhdl b/testsuite/gna/bug014/bug.vhdl new file mode 100644 index 000000000..bb0c4a1bf --- /dev/null +++ b/testsuite/gna/bug014/bug.vhdl @@ -0,0 +1,15 @@ +package pkg is + function f (a : integer) return integer; +end pkg; + +package body pkg is + function f (a : integer) return integer is + begin + return 1; + end f; + + function f (a : integer) return integer is + begin + return 1; + end f; +end pkg; diff --git a/testsuite/gna/bug014/bug2.vhdl b/testsuite/gna/bug014/bug2.vhdl new file mode 100644 index 000000000..4e03e6c04 --- /dev/null +++ b/testsuite/gna/bug014/bug2.vhdl @@ -0,0 +1,4 @@ +package pkg2 is + function f (a : integer) return integer; + function f (a : integer) return integer; +end pkg2; diff --git a/testsuite/gna/bug014/bug3.vhdl b/testsuite/gna/bug014/bug3.vhdl new file mode 100644 index 000000000..a94da5781 --- /dev/null +++ b/testsuite/gna/bug014/bug3.vhdl @@ -0,0 +1,7 @@ +package pkg3 is + function f (a : integer) return integer; + function f (a : integer) return integer is + begin + return 1; + end f; +end pkg3; diff --git a/testsuite/gna/bug014/testsuite.sh b/testsuite/gna/bug014/testsuite.sh new file mode 100755 index 000000000..27deff22e --- /dev/null +++ b/testsuite/gna/bug014/testsuite.sh @@ -0,0 +1,10 @@ +#! /bin/sh + +. ../../testenv.sh + +analyze_failure bug.vhdl +analyze_failure bug2.vhdl +analyze_failure bug3.vhdl +clean + +echo "Test successful" diff --git a/testsuite/gna/bug015/phys.vhdl b/testsuite/gna/bug015/phys.vhdl new file mode 100644 index 000000000..5af3359a4 --- /dev/null +++ b/testsuite/gna/bug015/phys.vhdl @@ -0,0 +1,24 @@ +package physical is + type FREQ is range 0 to INTEGER'high units + Hz; + kHz = 1000 Hz; + MHz = 1000 kHz; + GHz = 1000 MHz; +-- THz = 1000 GHz; + end units; +end package; + +entity tb is +end; + +use work.physical.all; + +architecture test of tb is + constant CLOCK_FREQ : FREQ := 100.0 MHz; + procedure p (a : freq := 1.0 Mhz) is + begin + end p; +begin + p (clock_freq); + -- empty +end architecture; diff --git a/testsuite/gna/bug015/phys2.vhdl b/testsuite/gna/bug015/phys2.vhdl new file mode 100644 index 000000000..3c0957fec --- /dev/null +++ b/testsuite/gna/bug015/phys2.vhdl @@ -0,0 +1,14 @@ +entity tb2 is +end; + +use work.physical.all; + +architecture test of tb2 is + constant CLOCK_FREQ : FREQ := MHz; + procedure p (a : freq) is + begin + end p; +begin + p (clock_freq); + -- empty +end architecture; diff --git a/testsuite/gna/bug015/testsuite.sh b/testsuite/gna/bug015/testsuite.sh new file mode 100755 index 000000000..59c4a42b3 --- /dev/null +++ b/testsuite/gna/bug015/testsuite.sh @@ -0,0 +1,12 @@ +#! /bin/sh + +. ../../testenv.sh + +analyze phys.vhdl +elab_simulate tb + +analyze phys2.vhdl +elab_simulate tb2 +clean + +echo "Test successful" diff --git a/testsuite/gna/bug016/pkg.vhdl b/testsuite/gna/bug016/pkg.vhdl new file mode 100644 index 000000000..21c115a31 --- /dev/null +++ b/testsuite/gna/bug016/pkg.vhdl @@ -0,0 +1,2 @@ +package pkg is +end pkg; diff --git a/testsuite/gna/bug016/repro.vhdl b/testsuite/gna/bug016/repro.vhdl new file mode 100644 index 000000000..d82cc5857 --- /dev/null +++ b/testsuite/gna/bug016/repro.vhdl @@ -0,0 +1,29 @@ +entity repro is +end repro; + +architecture behav of repro is + component comp is + port (s : bit); + end component; + signal s : bit; +begin + c : comp port map (s); +end behav; + +entity comp is + port (s : bit); +end comp; + +configuration conf of repro is + for behav + for c : comp + use entity work.compx (behav); + end for; + end for; +end conf; + +architecture behav of comp is +begin + assert s = '1'; +end behav; + diff --git a/testsuite/gna/bug016/repro1.vhdl b/testsuite/gna/bug016/repro1.vhdl new file mode 100644 index 000000000..655307968 --- /dev/null +++ b/testsuite/gna/bug016/repro1.vhdl @@ -0,0 +1,28 @@ +entity repro is +end repro; + +entity comp is + port (s : bit); +end comp; + +architecture behav of repro is + component comp is + port (s : bit); + end component; + signal s : bit; +begin + c : comp port map (s); +end behav; + +use work.pkg.all; +entity comp2 is + port (s : bit); +end comp2; + +architecture behav of comp is + component comp2 is + port (s : bit); + end component; +begin + c2: comp2 port map (s); +end behav; diff --git a/testsuite/gna/bug016/repro2.vhdl b/testsuite/gna/bug016/repro2.vhdl new file mode 100644 index 000000000..869197921 --- /dev/null +++ b/testsuite/gna/bug016/repro2.vhdl @@ -0,0 +1,18 @@ +configuration conf of repro is + for behav + for c : comp + use entity work.comp; + for behav + for c2 : comp2 + use entity work.comp2 (behav); + end for; + end for; + end for; + end for; +end conf; + +architecture behav of comp2 is +begin + assert s = '1'; +end behav; + diff --git a/testsuite/gna/bug016/testsuite.sh b/testsuite/gna/bug016/testsuite.sh new file mode 100755 index 000000000..5311492f1 --- /dev/null +++ b/testsuite/gna/bug016/testsuite.sh @@ -0,0 +1,14 @@ +#! /bin/sh + +. ../../testenv.sh + +analyze_failure repro.vhdl + +analyze pkg.vhdl +analyze repro1.vhdl +analyze pkg.vhdl +analyze_failure repro2.vhdl + +clean + +echo "Test successful" diff --git a/testsuite/gna/bug10/FIFO.vhdl b/testsuite/gna/bug10/FIFO.vhdl deleted file mode 100644 index e68a04e55..000000000 --- a/testsuite/gna/bug10/FIFO.vhdl +++ /dev/null @@ -1,69 +0,0 @@ -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity FIFO is - - generic(Depth : integer := 3); - - port( - iClk : in std_logic; - iReset : in std_logic; - -- write port - iWrEn : in std_logic; - iData : in std_logic_vector(7 downto 0); - oHasSpace : out std_logic; - -- read port - iRdEn : in std_logic; - oData : out std_logic_vector(7 downto 0); - oHasData : out std_logic - ); -end FIFO; - -architecture behaviour of FIFO is - - constant DMSB : integer := Depth - 1; - constant Size : integer := 2 ** DEPTH; - - type regArrayT is array(0 to Size-1) of std_logic_vector(7 downto 0); - - signal free : unsigned(Depth downto 0) := (others => '0'); - signal rIdx, wIdx : unsigned(DMSB downto 0) := (others => '0'); - signal regArray : regArrayT; - signal rdEn, wrEn : std_logic; - signal hasData, hasSpace : std_logic; - -begin - - oData <= regArray(to_integer(rIdx)); - hasData <= '0' when free = Size else '1'; - oHasData <= hasData; - - hasSpace <= '0' when free = to_unsigned(0, Depth) else '1'; - oHasSpace <= hasSpace; - - rdEn <= iRdEn and hasData; - wrEn <= iWrEn and hasSpace; - - main: process(iClk) begin - if iClk'event and iClk = '1' then - if iReset = '1' then - free <= to_unsigned(Size, Depth + 1); - rIdx <= (others => '0'); - wIdx <= (others => '0'); - elsif wrEn = '1' and rdEn = '1' then - rIdx <= rIdx + 1; - regArray(to_integer(wIdx)) <= iData; - wIdx <= wIdx + 1; - elsif rdEn = '1' then - rIdx <= rIdx + 1; - free <= free + 1; - elsif wrEn = '1' then - regArray(to_integer(wIdx)) <= iData; - wIdx <= wIdx + 1; - free <= free - 1; - end if; - end if; - end process; - -end behaviour; diff --git a/testsuite/gna/bug10/TestFIFO.vhdl b/testsuite/gna/bug10/TestFIFO.vhdl deleted file mode 100644 index c033172cd..000000000 --- a/testsuite/gna/bug10/TestFIFO.vhdl +++ /dev/null @@ -1,193 +0,0 @@ -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - --- equal speed writer and reader --- faster writer --- faster reader - -entity TestFIFO is -end TestFIFO; - - -architecture behaviour of TestFIFO is - - component FIFO is - generic(Depth : integer := 3); - port( - iClk : in std_logic; - iReset : in std_logic; - -- write port - iWrEn : in std_logic; - iData : in std_logic_vector(7 downto 0); - oHasSpace : out std_logic; - -- read port - iRdEn : in std_logic; - oData : out std_logic_vector(7 downto 0); - oHasData : out std_logic - ); - end component; - - type ramType is array(0 to 255) of std_logic_vector(7 downto 0); - - signal clk, reset : std_logic; - signal wrEn, rdEn : std_logic; - signal inData, outData : std_logic_vector(7 downto 0); - signal hasSpace, hasData : std_logic; - - signal rawInData : std_logic_vector(7 downto 0); - signal rawWrEn, rawRdEn : std_logic; - - signal dstRAM : ramType; - - signal writerData : unsigned(8 downto 0) := (others => '0'); - signal writerWrEn : std_logic; - signal writeDone : std_logic; - signal writerClkCntInit, readerClkCntInit : unsigned(1 downto 0) := "00"; - signal writerClkCnt, readerClkCnt : unsigned(1 downto 0) := "00"; - - signal readerCnt : unsigned(8 downto 0) := (others => '0'); - signal readerRdEn : std_logic; - signal readDone : std_logic; - - signal rawMode : std_logic; - - -begin - - FIFO0: FIFO port map( - iClk => clk, iReset => reset, - iWrEn => wrEn, iData => inData, oHasSpace => hasSpace, - iRdEn => rdEn, oData => outData, oHasData => hasData - ); - - wrEn <= rawWrEn when rawMode = '1' else writerWrEn; - rdEn <= rawRdEn when rawMode = '1' else readerRdEn; - - inData <= rawInData when rawMode = '1' else std_logic_vector(writerData(7 downto 0)); - writeDone <= writerData(7); -- done when writerData == 0x100 - writerWrEn <= '1' when (writerClkCnt = "00") and (hasSpace = '1') and (writeDone = '0') else '0'; - - fifoWriter: process(clk) - begin - if clk'event and clk = '1' and reset = '0' then - if writerClkCnt = "00" then - if hasSpace = '1' and writeDone = '0' then - writerData <= writerData + 1; - end if; - report "writerClkCnt <= writerClkCntInit;"; - writerClkCnt <= writerClkCntInit; - else - report "writerClkCnt <= writerClkCnt - 1;"; - writerClkCnt <= writerClkCnt - 1; - end if; - end if; - end process; - - readDone <= readerCnt(7); -- done when readerCnt == 0x100 - readerRdEn <= '1' when readerClkCnt = "00" and hasData = '1' and readDone = '0' else '0'; - - fifoReader: process(clk) - begin - if clk'event and clk = '1' and reset = '0' then - if readerClkCnt = "00" then - if hasData = '1' and readDone = '0' then - dstRAM(to_integer(readerCnt)) <= outData; - readerCnt <= readerCnt + 1; - end if; - readerClkCnt <= readerClkCntInit; - else - readerClkCnt <= readerClkCnt - 1; - end if; - end if; - end process; - - main: process - - procedure nextCycle is begin - wait for 500 ns; - report "rise"; - clk <= '1'; - wait for 500 ns; - clk <= '0'; - end procedure; - - procedure doReset is begin - reset <= '1'; - clk <= '0'; - nextCycle; - reset <= '0'; - end procedure; - - procedure testSimple is - - procedure write(data : std_logic_vector(7 downto 0); expHasData, expHasSpace: std_logic) is begin - rawWrEn <= '1'; - rawInData <= data; - nextCycle; - assert hasData = expHasData and hasSpace = expHasSpace; - end procedure; - - begin - rawMode <= '1'; - rawWrEn <= '0'; - rawRdEn <= '0'; - doReset; - assert hasData = '0' and hasSpace = '1'; - write(X"70", '1', '1'); - write(X"61", '1', '1'); - write(X"52", '1', '1'); - write(X"43", '1', '1'); - write(X"34", '1', '1'); - write(X"25", '1', '1'); - write(X"16", '1', '1'); - write(X"07", '1', '0'); - write(X"5a", '1', '0'); -- attempt to write to the full FIFO, should be ignored - end procedure; - - procedure clearDst is - variable i : integer; - begin - for i in 0 to 255 loop - dstRAM(i) <= X"00"; - end loop; - end procedure; - - procedure checkDst is - variable i : integer; - begin - for i in 0 to 255 loop - assert dstRAM(i) = std_logic_vector(to_unsigned(i, 8)); - end loop; - end procedure; - - -- 0 means fastest - procedure setWriterSpeed(div: integer) is begin - writerClkCntInit <= to_unsigned(div, 2); - writerClkCnt <= to_unsigned(div, 2); - writerData <= (others => '0'); - end procedure; - - procedure setReaderSpeed(div: integer) is begin - readerClkCntInit <= to_unsigned(div, 2); - readerClkCnt <= to_unsigned(div, 2); - end procedure; - - procedure testEqualFastSpeed is begin - setWriterSpeed(0); - setReaderSpeed(0); - clearDst; - doReset; - while readDone = '0' loop - nextCycle; - end loop; - checkDst; - end procedure; - - begin - testSimple; - -- testEqualFastSpeed; - wait; -- wait forever, end simulation - end process; - -end behaviour; diff --git a/testsuite/gna/bug10/testsuite.sh b/testsuite/gna/bug10/testsuite.sh deleted file mode 100755 index 2c649ecef..000000000 --- a/testsuite/gna/bug10/testsuite.sh +++ /dev/null @@ -1,10 +0,0 @@ -#! /bin/sh - -. ../../testenv.sh - -analyze FIFO.vhdl TestFIFO.vhdl -elab_simulate testfifo --stop-time=4us - -clean - -echo "Test successful" diff --git a/testsuite/gna/bug11/phonybench.vhdl b/testsuite/gna/bug11/phonybench.vhdl deleted file mode 100644 index 040980454..000000000 --- a/testsuite/gna/bug11/phonybench.vhdl +++ /dev/null @@ -1,59 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity phonybench is - generic ( - GENSTR : string := "adrien"; - GENSTDLV : std_logic_vector(5 downto 0) := "111000"; - GENSTDL : std_logic := '1'; - GENNAT : natural := 22 - ); -end phonybench; - -architecture bench of phonybench is - - type char2std_t is array(character) of std_ulogic; - - constant char2std_c : char2std_t := ( - 'U' => 'U', - 'X' => 'X', - '0' => '0', - '1' => '1', - 'Z' => 'Z', - 'W' => 'W', - 'L' => 'L', - 'H' => 'H', - '-' => '-', - others => 'X' - ); - - function str2std(arg : string) return std_logic_vector is - variable result : std_logic_vector(arg'length - 1 downto 0); - variable j : integer; - begin - j := arg'length - 1; - for i in arg'range loop - result(j) := char2std_c(arg(i)); - j := j - 1; - end loop; - return result; - end function; - - signal sigvec1 : std_logic_vector(5 downto 0) := str2std(GENSTR); - signal sigvec2 : std_logic_vector(5 downto 0) := GENSTDLV; - signal siglog : std_logic := GENSTDL; - signal signat : natural := GENNAT; - - signal clk : std_logic := '0'; - -begin - - clk <= not clk after 5 ms; - - sigvec1 <= str2std(GENSTR); - sigvec2 <= GENSTDLV; - siglog <= GENSTDL; - signat <= GENNAT; - -end architecture; diff --git a/testsuite/gna/bug11/testsuite.sh b/testsuite/gna/bug11/testsuite.sh deleted file mode 100755 index 5823c99d5..000000000 --- a/testsuite/gna/bug11/testsuite.sh +++ /dev/null @@ -1,12 +0,0 @@ -#! /bin/sh - -. ../../testenv.sh - -analyze phonybench.vhdl -elab_simulate phonybench --stop-time=1sec --fst=pb.fst - -rm -f pb.fst pb.ghw - -clean - -echo "Test successful" diff --git a/testsuite/gna/bug12/demo.vhd b/testsuite/gna/bug12/demo.vhd deleted file mode 100644 index 2b97782f6..000000000 --- a/testsuite/gna/bug12/demo.vhd +++ /dev/null @@ -1,14 +0,0 @@ -entity bar is -end entity bar; -entity \foo\ is - port (test : in bit); -end entity \foo\; -architecture structural of \foo\ is -begin -- architecture structural -end architecture structural; -architecture structural of bar is - signal test : bit; -begin -- architecture structural - foo_1: entity work.\foo\ - port map (test => test); -end architecture structural; diff --git a/testsuite/gna/bug12/testsuite.sh b/testsuite/gna/bug12/testsuite.sh deleted file mode 100755 index 9b3d98c20..000000000 --- a/testsuite/gna/bug12/testsuite.sh +++ /dev/null @@ -1,10 +0,0 @@ -#! /bin/sh - -. ../../testenv.sh - -analyze demo.vhd -elab_simulate bar structural - -clean - -echo "Test successful" diff --git a/testsuite/gna/bug14/bug.vhdl b/testsuite/gna/bug14/bug.vhdl deleted file mode 100644 index bb0c4a1bf..000000000 --- a/testsuite/gna/bug14/bug.vhdl +++ /dev/null @@ -1,15 +0,0 @@ -package pkg is - function f (a : integer) return integer; -end pkg; - -package body pkg is - function f (a : integer) return integer is - begin - return 1; - end f; - - function f (a : integer) return integer is - begin - return 1; - end f; -end pkg; diff --git a/testsuite/gna/bug14/bug2.vhdl b/testsuite/gna/bug14/bug2.vhdl deleted file mode 100644 index 4e03e6c04..000000000 --- a/testsuite/gna/bug14/bug2.vhdl +++ /dev/null @@ -1,4 +0,0 @@ -package pkg2 is - function f (a : integer) return integer; - function f (a : integer) return integer; -end pkg2; diff --git a/testsuite/gna/bug14/bug3.vhdl b/testsuite/gna/bug14/bug3.vhdl deleted file mode 100644 index a94da5781..000000000 --- a/testsuite/gna/bug14/bug3.vhdl +++ /dev/null @@ -1,7 +0,0 @@ -package pkg3 is - function f (a : integer) return integer; - function f (a : integer) return integer is - begin - return 1; - end f; -end pkg3; diff --git a/testsuite/gna/bug14/testsuite.sh b/testsuite/gna/bug14/testsuite.sh deleted file mode 100755 index 27deff22e..000000000 --- a/testsuite/gna/bug14/testsuite.sh +++ /dev/null @@ -1,10 +0,0 @@ -#! /bin/sh - -. ../../testenv.sh - -analyze_failure bug.vhdl -analyze_failure bug2.vhdl -analyze_failure bug3.vhdl -clean - -echo "Test successful" diff --git a/testsuite/gna/bug15/phys.vhdl b/testsuite/gna/bug15/phys.vhdl deleted file mode 100644 index 5af3359a4..000000000 --- a/testsuite/gna/bug15/phys.vhdl +++ /dev/null @@ -1,24 +0,0 @@ -package physical is - type FREQ is range 0 to INTEGER'high units - Hz; - kHz = 1000 Hz; - MHz = 1000 kHz; - GHz = 1000 MHz; --- THz = 1000 GHz; - end units; -end package; - -entity tb is -end; - -use work.physical.all; - -architecture test of tb is - constant CLOCK_FREQ : FREQ := 100.0 MHz; - procedure p (a : freq := 1.0 Mhz) is - begin - end p; -begin - p (clock_freq); - -- empty -end architecture; diff --git a/testsuite/gna/bug15/phys2.vhdl b/testsuite/gna/bug15/phys2.vhdl deleted file mode 100644 index 3c0957fec..000000000 --- a/testsuite/gna/bug15/phys2.vhdl +++ /dev/null @@ -1,14 +0,0 @@ -entity tb2 is -end; - -use work.physical.all; - -architecture test of tb2 is - constant CLOCK_FREQ : FREQ := MHz; - procedure p (a : freq) is - begin - end p; -begin - p (clock_freq); - -- empty -end architecture; diff --git a/testsuite/gna/bug15/testsuite.sh b/testsuite/gna/bug15/testsuite.sh deleted file mode 100755 index 59c4a42b3..000000000 --- a/testsuite/gna/bug15/testsuite.sh +++ /dev/null @@ -1,12 +0,0 @@ -#! /bin/sh - -. ../../testenv.sh - -analyze phys.vhdl -elab_simulate tb - -analyze phys2.vhdl -elab_simulate tb2 -clean - -echo "Test successful" diff --git a/testsuite/gna/bug16/pkg.vhdl b/testsuite/gna/bug16/pkg.vhdl deleted file mode 100644 index 21c115a31..000000000 --- a/testsuite/gna/bug16/pkg.vhdl +++ /dev/null @@ -1,2 +0,0 @@ -package pkg is -end pkg; diff --git a/testsuite/gna/bug16/repro.vhdl b/testsuite/gna/bug16/repro.vhdl deleted file mode 100644 index d82cc5857..000000000 --- a/testsuite/gna/bug16/repro.vhdl +++ /dev/null @@ -1,29 +0,0 @@ -entity repro is -end repro; - -architecture behav of repro is - component comp is - port (s : bit); - end component; - signal s : bit; -begin - c : comp port map (s); -end behav; - -entity comp is - port (s : bit); -end comp; - -configuration conf of repro is - for behav - for c : comp - use entity work.compx (behav); - end for; - end for; -end conf; - -architecture behav of comp is -begin - assert s = '1'; -end behav; - diff --git a/testsuite/gna/bug16/repro1.vhdl b/testsuite/gna/bug16/repro1.vhdl deleted file mode 100644 index 655307968..000000000 --- a/testsuite/gna/bug16/repro1.vhdl +++ /dev/null @@ -1,28 +0,0 @@ -entity repro is -end repro; - -entity comp is - port (s : bit); -end comp; - -architecture behav of repro is - component comp is - port (s : bit); - end component; - signal s : bit; -begin - c : comp port map (s); -end behav; - -use work.pkg.all; -entity comp2 is - port (s : bit); -end comp2; - -architecture behav of comp is - component comp2 is - port (s : bit); - end component; -begin - c2: comp2 port map (s); -end behav; diff --git a/testsuite/gna/bug16/repro2.vhdl b/testsuite/gna/bug16/repro2.vhdl deleted file mode 100644 index 869197921..000000000 --- a/testsuite/gna/bug16/repro2.vhdl +++ /dev/null @@ -1,18 +0,0 @@ -configuration conf of repro is - for behav - for c : comp - use entity work.comp; - for behav - for c2 : comp2 - use entity work.comp2 (behav); - end for; - end for; - end for; - end for; -end conf; - -architecture behav of comp2 is -begin - assert s = '1'; -end behav; - diff --git a/testsuite/gna/bug16/testsuite.sh b/testsuite/gna/bug16/testsuite.sh deleted file mode 100755 index 5311492f1..000000000 --- a/testsuite/gna/bug16/testsuite.sh +++ /dev/null @@ -1,14 +0,0 @@ -#! /bin/sh - -. ../../testenv.sh - -analyze_failure repro.vhdl - -analyze pkg.vhdl -analyze repro1.vhdl -analyze pkg.vhdl -analyze_failure repro2.vhdl - -clean - -echo "Test successful" diff --git a/testsuite/gna/testsuite.sh b/testsuite/gna/testsuite.sh index f4240a058..75f3c3ab1 100755 --- a/testsuite/gna/testsuite.sh +++ b/testsuite/gna/testsuite.sh @@ -4,7 +4,8 @@ # Each test correspond to one report, and is put in one directory (using # the support/bug number) # -# bugXXX is for bugs reported on https://gna.org/bugs/?group=ghdl +# bug0XX is for bugs not reported. +# bug[1-9]XXX is for bugs reported on https://gna.org/bugs/?group=ghdl # srXXX is for support reported on https://gna.org/support/?group=ghdl # debXX is for bugs report on http://bugs.debian.org/ # ticketXX is from https://sourceforge.net/p/ghdl-updates/tickets/ -- cgit v1.2.3