From 78b2738b38390bdb2535d738973e2cf17e23ef4c Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Mon, 1 May 2023 10:12:12 +0200
Subject: testsuite/gna: add a test for previous commit

---
 testsuite/gna/issue2422/aggr_repro1.vhdl | 36 ++++++++++++++++++++++++++
 testsuite/gna/issue2422/aggr_repro2.vhdl | 36 ++++++++++++++++++++++++++
 testsuite/gna/issue2422/aggr_repro3.vhdl | 34 +++++++++++++++++++++++++
 testsuite/gna/issue2422/aggr_repro4.vhdl | 43 ++++++++++++++++++++++++++++++++
 testsuite/gna/issue2422/testsuite.sh     | 27 ++++++++++++++++++++
 5 files changed, 176 insertions(+)
 create mode 100644 testsuite/gna/issue2422/aggr_repro1.vhdl
 create mode 100644 testsuite/gna/issue2422/aggr_repro2.vhdl
 create mode 100644 testsuite/gna/issue2422/aggr_repro3.vhdl
 create mode 100644 testsuite/gna/issue2422/aggr_repro4.vhdl
 create mode 100755 testsuite/gna/issue2422/testsuite.sh

(limited to 'testsuite/gna')

diff --git a/testsuite/gna/issue2422/aggr_repro1.vhdl b/testsuite/gna/issue2422/aggr_repro1.vhdl
new file mode 100644
index 000000000..14540a47b
--- /dev/null
+++ b/testsuite/gna/issue2422/aggr_repro1.vhdl
@@ -0,0 +1,36 @@
+library ieee;
+use     ieee.std_logic_1164.all;
+use     ieee.numeric_std.all;
+
+entity comp_repro1 is
+	port (
+		output : out unsigned
+	);
+end entity;
+
+architecture a1 of comp_repro1 is
+begin
+	output <= (7 downto 0 => '0');  -- not using others due to issue #2421
+end architecture;
+
+
+entity aggr_repro1 is
+end;
+
+library ieee;
+use     ieee.std_logic_1164.all;
+use     ieee.numeric_std.all;
+
+architecture behav of aggr_repro1 is
+  signal s : unsigned(7 downto 0);
+begin
+  inst: entity work.comp_repro1
+    port map (output => s);
+
+  process
+  begin
+    wait for 1 ns;
+    assert s = (s'range => '0') severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/gna/issue2422/aggr_repro2.vhdl b/testsuite/gna/issue2422/aggr_repro2.vhdl
new file mode 100644
index 000000000..910b7fa9c
--- /dev/null
+++ b/testsuite/gna/issue2422/aggr_repro2.vhdl
@@ -0,0 +1,36 @@
+library ieee;
+use     ieee.std_logic_1164.all;
+use     ieee.numeric_std.all;
+
+entity comp_repro2 is
+	port (
+		output : out unsigned
+	);
+end entity;
+
+architecture a1 of comp_repro2 is
+begin
+	output <= (others => '0');  -- not using others due to issue #2421
+end architecture;
+
+
+entity aggr_repro2 is
+end;
+
+library ieee;
+use     ieee.std_logic_1164.all;
+use     ieee.numeric_std.all;
+
+architecture behav of aggr_repro2 is
+  signal s : unsigned(7 downto 0);
+begin
+  inst: entity work.comp_repro2
+    port map (output => s);
+
+  process
+  begin
+    wait for 1 ns;
+    assert s = (s'range => '0') severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/gna/issue2422/aggr_repro3.vhdl b/testsuite/gna/issue2422/aggr_repro3.vhdl
new file mode 100644
index 000000000..3f3f95c89
--- /dev/null
+++ b/testsuite/gna/issue2422/aggr_repro3.vhdl
@@ -0,0 +1,34 @@
+library ieee;
+use     ieee.std_logic_1164.all;
+
+entity comp_repro3 is
+	port (
+		output : out std_logic_vector
+	);
+end entity;
+
+architecture a1 of comp_repro3 is
+begin
+	output <= (7 downto 0 => '0');  -- not using others due to issue #2421
+end architecture;
+
+
+entity aggr_repro3 is
+end;
+
+library ieee;
+use     ieee.std_logic_1164.all;
+
+architecture behav of aggr_repro3 is
+  signal s : std_logic_vector(7 downto 0);
+begin
+  inst: entity work.comp_repro3
+    port map (output => s);
+
+  process
+  begin
+    wait for 1 ns;
+    assert s = (s'range => '0') severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/gna/issue2422/aggr_repro4.vhdl b/testsuite/gna/issue2422/aggr_repro4.vhdl
new file mode 100644
index 000000000..bd474730f
--- /dev/null
+++ b/testsuite/gna/issue2422/aggr_repro4.vhdl
@@ -0,0 +1,43 @@
+library ieee;
+use     ieee.std_logic_1164.all;
+
+package pkg_repro4 is
+  subtype my_slv is std_ulogic_vector;
+end;
+
+library ieee;
+use     ieee.std_logic_1164.all;
+use work.pkg_repro4.all;
+
+entity comp_repro4 is
+	port (
+		output : out my_slv
+	);
+end entity;
+
+architecture a1 of comp_repro4 is
+begin
+	output <= (7 downto 0 => '0');  -- not using others due to issue #2421
+end architecture;
+
+
+entity aggr_repro4 is
+end;
+
+library ieee;
+use     ieee.std_logic_1164.all;
+use work.pkg_repro4.all;
+
+architecture behav of aggr_repro4 is
+  signal s : my_slv(7 downto 0);
+begin
+  inst: entity work.comp_repro4
+    port map (output => s);
+
+  process
+  begin
+    wait for 1 ns;
+    assert s = (s'range => '0') severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/gna/issue2422/testsuite.sh b/testsuite/gna/issue2422/testsuite.sh
new file mode 100755
index 000000000..19b226075
--- /dev/null
+++ b/testsuite/gna/issue2422/testsuite.sh
@@ -0,0 +1,27 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=93
+analyze aggr_repro1.vhdl
+elab_simulate aggr_repro1
+
+analyze aggr_repro3.vhdl
+elab_simulate aggr_repro3
+
+analyze aggr_repro4.vhdl
+elab_simulate aggr_repro4
+
+export GHDL_STD_FLAGS=--std=93c
+analyze aggr_repro2.vhdl
+elab_simulate aggr_repro2
+
+clean
+
+#export GHDL_STD_FLAGS=--std=08
+#analyze repro.vhdl
+#elab_simulate repro
+
+#clean
+
+echo "Test successful"
-- 
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