From 19689779317783c8d44e41111e73ed37c6307dd6 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Thu, 11 Aug 2022 21:15:22 +0200
Subject: testsuite/gna: add tests for #2174

---
 testsuite/gna/issue2174/t1.vhdl      |  9 +++++++++
 testsuite/gna/issue2174/t2.vhdl      | 19 +++++++++++++++++++
 testsuite/gna/issue2174/t3.vhdl      | 19 +++++++++++++++++++
 testsuite/gna/issue2174/test.vhdl    | 19 +++++++++++++++++++
 testsuite/gna/issue2174/testsuite.sh | 14 ++++++++++++++
 5 files changed, 80 insertions(+)
 create mode 100644 testsuite/gna/issue2174/t1.vhdl
 create mode 100644 testsuite/gna/issue2174/t2.vhdl
 create mode 100644 testsuite/gna/issue2174/t3.vhdl
 create mode 100644 testsuite/gna/issue2174/test.vhdl
 create mode 100755 testsuite/gna/issue2174/testsuite.sh

(limited to 'testsuite/gna')

diff --git a/testsuite/gna/issue2174/t1.vhdl b/testsuite/gna/issue2174/t1.vhdl
new file mode 100644
index 000000000..124d4605c
--- /dev/null
+++ b/testsuite/gna/issue2174/t1.vhdl
@@ -0,0 +1,9 @@
+use std.textio.all;
+
+entity t1 is
+end;
+
+architecture behav of t1 is
+  subtype stext is text;
+begin
+end behav;
diff --git a/testsuite/gna/issue2174/t2.vhdl b/testsuite/gna/issue2174/t2.vhdl
new file mode 100644
index 000000000..b1449665c
--- /dev/null
+++ b/testsuite/gna/issue2174/t2.vhdl
@@ -0,0 +1,19 @@
+use std.textio.all;
+
+entity t2 is
+end;
+
+architecture behav of t2 is
+  subtype stext is text;
+
+  procedure w (file f : stext; s : string) is
+  begin
+    write (f, s);
+  end w;
+begin
+  process
+  begin
+    w (output, "hello" & LF);
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/gna/issue2174/t3.vhdl b/testsuite/gna/issue2174/t3.vhdl
new file mode 100644
index 000000000..ba715a92a
--- /dev/null
+++ b/testsuite/gna/issue2174/t3.vhdl
@@ -0,0 +1,19 @@
+use std.textio.all;
+
+entity t3 is
+end;
+
+architecture behav of t3 is
+  subtype stext is text;
+
+  procedure w (file f : text; s : string) is
+  begin
+    write (f, s);
+  end w;
+begin
+  process
+  begin
+    w (output, "hello" & LF);
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/gna/issue2174/test.vhdl b/testsuite/gna/issue2174/test.vhdl
new file mode 100644
index 000000000..fc196e458
--- /dev/null
+++ b/testsuite/gna/issue2174/test.vhdl
@@ -0,0 +1,19 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use std.textio.all;
+
+package sim_ram_pkg is
+
+    subtype lol is text;
+    
+    type sim_ram is record
+        fid: lol;
+    end record sim_ram;
+
+end sim_ram_pkg;
+
+package body sim_ram_pkg is
+
+end package body sim_ram_pkg;
diff --git a/testsuite/gna/issue2174/testsuite.sh b/testsuite/gna/issue2174/testsuite.sh
new file mode 100755
index 000000000..b59e7f7da
--- /dev/null
+++ b/testsuite/gna/issue2174/testsuite.sh
@@ -0,0 +1,14 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+analyze_failure test.vhdl
+
+for e in t1 t2 t3; do
+    analyze $e.vhdl
+    elab_simulate $e
+done
+
+clean
+
+echo "Test successful"
-- 
cgit v1.2.3